Add AND(register) and AND(immediate) to ARM integrated assembler.

src/DartARM32/assembler_arm.cc

@@ -185,10 +185,12 @@ void Assembler::EmitShiftRegister(Condition cond,
 }
 
 
+#if 0
+// Moved to ARM32::AssemblerARM32::and_()
 void Assembler::and_(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), AND, 0, rn, rd, o);
 }
-
+#endif
 
 void Assembler::eor(Register rd, Register rn, Operand o, Condition cond) {
   EmitType01(cond, o.type(), EOR, 0, rn, rd, o);

src/DartARM32/assembler_arm.h

@@ -438,8 +438,11 @@ class Assembler : public ValueObject {
 
   static const char* FpuRegisterName(FpuRegister reg);
 
+#if 0
+  // Moved to ARM32::AssemblerARM32::and_()
   // Data-processing instructions.
   void and_(Register rd, Register rn, Operand o, Condition cond = AL);
+#endif
 
   void eor(Register rd, Register rn, Operand o, Condition cond = AL);
 

src/IceAssemblerARM32.cpp

@@ -465,7 +465,51 @@ void AssemblerARM32::add(const Operand *OpRd, const Operand *OpRn,
     emitType01(Cond, kInstTypeDataImmediate, Add, SetFlags, Rn, Rd, Src1Value);
     return;
   }
-  };
+  }
+}
+
+void AssemblerARM32::and_(const Operand *OpRd, const Operand *OpRn,
+                          const Operand *OpSrc1, bool SetFlags,
+                          CondARM32::Cond Cond) {
+  IValueT Rd;
+  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  IValueT Rn;
+  if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  constexpr IValueT And = 0; // 0000
+  IValueT Src1Value;
+  // TODO(kschimpf) Other possible decodings of add.
+  switch (decodeOperand(OpSrc1, Src1Value)) {
+  default:
+    return setNeedsTextFixup();
+  case DecodedAsRegister: {
+    // AND (register) - ARM section A8.8.14, encoding A1:
+    //   and{s}<c> <Rd>, <Rn>{, <shift>}
+    //
+    // cccc0000000snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
+    // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
+    constexpr IValueT Imm5 = 0;
+    Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Imm5);
+    if (((Rd == RegARM32::Encoded_Reg_pc) && SetFlags))
+      // Conditions of rule violated.
+      return setNeedsTextFixup();
+    emitType01(Cond, kInstTypeDataRegister, And, SetFlags, Rn, Rd, Src1Value);
+    return;
+  }
+  case DecodedAsRotatedImm8: {
+    // AND (Immediate) - ARM section A8.8.13, encoding A1:
+    //   and{s}<c> <Rd>, <Rn>, #<RotatedImm8>
+    //
+    // cccc0010100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
+    // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
+    if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
+      // Conditions of rule violated.
+      return setNeedsTextFixup();
+    emitType01(Cond, kInstTypeDataImmediate, And, SetFlags, Rn, Rd, Src1Value);
+    return;
+  }
+  }
 }
 
 void AssemblerARM32::b(Label *L, CondARM32::Cond Cond) {

src/IceAssemblerARM32.h

@@ -141,6 +141,9 @@ public:
   void add(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 
+  void and_(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
+            bool SetFlags, CondARM32::Cond Cond);
+
   void b(Label *L, CondARM32::Cond Cond);
 
   void bkpt(uint16_t Imm16);

src/IceInstARM32.cpp

@@ -360,6 +360,13 @@ void InstARM32ThreeAddrGPR<InstARM32::Add>::emitIAS(const Cfg *Func) const {
     emitUsingTextFixup(Func);
 }
 
+template <> void InstARM32And::emitIAS(const Cfg *Func) const {
+  ARM32::AssemblerARM32 *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  Asm->and_(getDest(), getSrc(0), getSrc(1), SetFlags, getPredicate());
+  if (Asm->needsTextFixup())
+    emitUsingTextFixup(Func);
+}
+
 template <>
 void InstARM32ThreeAddrGPR<InstARM32::Sbc>::emitIAS(const Cfg *Func) const {
   ARM32::AssemblerARM32 *Asm = Func->getAssembler<ARM32::AssemblerARM32>();

tests_lit/assembler/arm32/and.ll

+; Show that we know how to translate and.
+
+; NOTE: We use -O2 to get rid of memory stores.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
+
+define internal i32 @And1WithR0(i32 %p) {
+  %v = and i32 %p, 1
+  ret i32 %v
+}
+
+; ASM-LABEL:And1WithR0:
+; ASM-NEXT:.LAnd1WithR0$__0:
+; ASM-NEXT:     and     r0, r0, #1
+
+; DIS-LABEL:00000000 <And1WithR0>:
+; DIS-NEXT:   0:        e2000001
+
+; IASM-LABEL:And1WithR0:
+; IASM-NEXT:.LAnd1WithR0$__0:
+; IASM-NEXT:     .byte 0x1
+; IASM-NEXT:     .byte 0x0
+; IASM-NEXT:     .byte 0x0
+; IASM-NEXT:     .byte 0xe2
+
+define internal i32 @And2Regs(i32 %p1, i32 %p2) {
+  %v = and i32 %p1, %p2
+  ret i32 %v
+}
+
+; ASM-LABEL:And2Regs:
+; ASM-NEXT:.LAnd2Regs$__0:
+; ASM-NEXT:     and     r0, r0, r1
+
+; DIS-LABEL:00000010 <And2Regs>:
+; DIS-NEXT:  10:        e0000001
+
+; IASM-LABEL:And2Regs:
+; IASM-NEXT:.LAnd2Regs$__0:
+; IASM-NEXT:     .byte 0x1
+; IASM-NEXT:     .byte 0x0
+; IASM-NEXT:     .byte 0x0
+; IASM-NEXT:     .byte 0xe0
+
+define internal i64 @AndI64WithR0R1(i64 %p) {
+  %v = and i64 %p, 1
+  ret i64 %v
+}
+
+; ASM-LABEL:AndI64WithR0R1:
+; ASM-NEXT:.LAndI64WithR0R1$__0:
+; ASM-NEXT:     and     r0, r0, #1
+; ASM-NEXT:     and     r1, r1, #0
+
+; DIS-LABEL:00000020 <AndI64WithR0R1>:
+; DIS-NEXT:  20:        e2000001
+; DIS-NEXT:  24:        e2011000
+
+; IASM-LABEL:AndI64WithR0R1:
+; IASM-NEXT:.LAndI64WithR0R1$__0:
+; IASM-NEXT:     .byte 0x1
+; IASM-NEXT:     .byte 0x0
+; IASM-NEXT:     .byte 0x0
+; IASM-NEXT:     .byte 0xe2
+; IASM-NEXT:     .byte 0x0
+; IASM-NEXT:     .byte 0x10
+; IASM-NEXT:     .byte 0x1
+; IASM-NEXT:     .byte 0xe2
+
+define internal i64 @AndI64Regs(i64 %p1, i64 %p2) {
+  %v = and i64 %p1, %p2
+  ret i64 %v
+}
+
+; ASM-LABEL:AndI64Regs:
+; ASM-NEXT:.LAndI64Regs$__0:
+; ASM-NEXT:     and     r0, r0, r2
+; ASM-NEXT:     and     r1, r1, r3
+
+; DIS-LABEL:00000030 <AndI64Regs>:
+; DIS-NEXT:  30:        e0000002
+; DIS-NEXT:  34:        e0011003
+
+; IASM-LABEL:AndI64Regs:
+; IASM-NEXT:.LAndI64Regs$__0:
+; IASM-NEXT:     .byte 0x2
+; IASM-NEXT:     .byte 0x0
+; IASM-NEXT:     .byte 0x0
+; IASM-NEXT:     .byte 0xe0
+; IASM-NEXT:     .byte 0x3
+; IASM-NEXT:     .byte 0x10
+; IASM-NEXT:     .byte 0x1
+; IASM-NEXT:     .byte 0xe0