[Subzero][MIPS] Fix test nacl-other-intrinsics.ll

The test nacl-other-intrinsics.ll fails with an assertion failure: assert(SpillAreaAlignmentBytes <= MIPS32_STACK_ALIGNMENT_BYTES). This assertion triggers because MIPS32_STACK_ALIGNMENT_BYTES is 8 and SpillAreaAlignmentBytes is 16. The minimum required alignment of stack for MIPS32 is 8 bytes according to the ABI document. Since 16 is aligned to 8, we can safely keep the stack aligned to 16 bytes to fix the test. R=stichnot@chromium.org Review URL: https://codereview.chromium.org/2339683003 . Patch from Sagar Thakur <sagar.thakur@imgtec.com>.

[Subzero][MIPS] Fix test nacl-other-intrinsics.ll
ccbb6d16 · Sagar Thakur · Jim Stichnoth · d57ed5fa · ccbb6d16 · ccbb6d16
Commit ccbb6d16 authored Sep 14, 2016 by Sagar Thakur Committed by Jim Stichnoth Sep 14, 2016
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IceTargetLoweringMIPS32.cpp src/IceTargetLoweringMIPS32.cpp +1 -1

alloc.ll tests_lit/llvm2ice_tests/alloc.ll +14 -14

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--- a/src/IceTargetLoweringMIPS32.cpp
+++ b/src/IceTargetLoweringMIPS32.cpp
@@ -84,7 +84,7 @@ const char *getRegClassName(RegClass C) {
 }

 // Stack alignment
-constexpr uint32_t MIPS32_STACK_ALIGNMENT_BYTES = 8;
+constexpr uint32_t MIPS32_STACK_ALIGNMENT_BYTES = 16;

 // Value is in bytes. Return Value adjusted to the next highest multiple of the
 // stack alignment required for the given type.

--- a/tests_lit/llvm2ice_tests/alloc.ll
+++ b/tests_lit/llvm2ice_tests/alloc.ll
@@ -65,7 +65,7 @@ entry:
 ; ARM32:       bl {{.*}} R_{{.*}}    f1

 ; MIPS32-LABEL: fixed_416_align_16
-; MIPS32-OPT2: addiu sp,sp,-440
+; MIPS32-OPT2: addiu sp,sp,-448
 ; MIPS32-OPT2: addiu a0,sp,16
 ; MIPS32-OPTM1: addiu sp,sp,-448
 ; MIPS32-OPTM1: addiu [[REG:.*]],sp,16
@@ -96,7 +96,7 @@ entry:
 ; ARM32:       bl {{.*}} R_{{.*}}    f1

 ; MIPS32-LABEL: fixed_416_align_32
-; MIPS32-OPT2: addiu sp,sp,-440
+; MIPS32-OPT2: addiu sp,sp,-448
 ; MIPS32-OPT2: addiu a0,sp,16
 ; MIPS32-OPTM1: addiu sp,sp,-448
 ; MIPS32-OPTM1: addiu [[REG:.*]],sp,16
@@ -130,7 +130,7 @@ entry:
 ; ARM32:       bl {{.*}} R_{{.*}}    f1

 ; MIPS32-LABEL: fixed_351_align_16
-; MIPS32-OPT2: addiu sp,sp,-376
+; MIPS32-OPT2: addiu sp,sp,-384
 ; MIPS32-OPT2: addiu a0,sp,16
 ; MIPS32-OPTM1: addiu sp,sp,-384
 ; MIPS32-OPTM1: addiu [[REG:.*]],sp,16
@@ -161,7 +161,7 @@ entry:
 ; ARM32:       bl {{.*}} R_{{.*}}    f1

 ; MIPS32-LABEL: fixed_351_align_32
-; MIPS32-OPT2: addiu sp,sp,-376
+; MIPS32-OPT2: addiu sp,sp,-384
 ; MIPS32-OPT2: addiu a0,sp,16
 ; MIPS32-OPTM1: addiu sp,sp,-384
 ; MIPS32-OPTM1: addiu [[REG:.*]],sp,16
@@ -197,8 +197,8 @@ entry:
 ; ARM32:      bl {{.*}} R_{{.*}}    f2

 ; MIPS32-LABEL: variable_n_align_16
-; MIPS32: addiu	[[REG:.*]],{{.*}},7
-; MIPS32: li	[[REG1:.*]],-8
+; MIPS32: addiu	[[REG:.*]],{{.*}},15
+; MIPS32: li	[[REG1:.*]],-16
 ; MIPS32: and	[[REG2:.*]],[[REG]],[[REG1]]
 ; MIPS32: subu	[[REG3:.*]],sp,[[REG2:.*]]
 ; MIPS32: li	[[REG4:.*]],-16
@@ -242,8 +242,8 @@ entry:
 ; ARM32:      pop {fp, lr}

 ; MIPS32-LABEL: variable_n_align_32
-; MIPS32: addiu	[[REG:.*]],{{.*}},7
-; MIPS32: li 	[[REG1:.*]],-8
+; MIPS32: addiu	[[REG:.*]],{{.*}},15
+; MIPS32: li 	[[REG1:.*]],-16
 ; MIPS32: and 	[[REG2:.*]],[[REG]],[[REG1]]
 ; MIPS32: subu 	[[REG3:.*]],sp,[[REG2]]
 ; MIPS32: li 	[[REG4:.*]],-32
@@ -271,8 +271,8 @@ entry:
 ; ARM32: sub sp, sp, r0

 ; MIPS32-LABEL: align0
-; MIPS32: addiu	[[REG:.*]],{{.*}},7
-; MIPS32: li	[[REG1:.*]],-8
+; MIPS32: addiu	[[REG:.*]],{{.*}},15
+; MIPS32: li	[[REG1:.*]],-16
 ; MIPS32: and	[[REG2:.*]],[[REG]],[[REG1]]
 ; MIPS32: subu	{{.*}},sp,[[REG2]]
 ; MIPS32: addiu	sp,sp,-16
@@ -309,8 +309,8 @@ entry:
 ; ARM32: sub sp, sp, r0

 ; MIPS32-LABEL: align1MB
-; MIPS32: addiu	[[REG:.*]],{{.*}},7
-; MIPS32: li	[[REG1:.*]],-8
+; MIPS32: addiu	[[REG:.*]],{{.*}},15
+; MIPS32: li	[[REG1:.*]],-16
 ; MIPS32: and	[[REG2:.*]],[[REG]],[[REG1]]
 ; MIPS32: subu	[[REG3:.*]],sp,[[REG2]]
 ; MIPS32: lui	[[REG4:.*]],0xfff0
@@ -344,8 +344,8 @@ entry:
 ; ARM32: sub sp, sp, r0

 ; MIPS32-LABEL: align512MB
-; MIPS32: addiu	[[REG:.*]],{{.*}},7
-; MIPS32: li	[[REG2:.*]],-8
+; MIPS32: addiu	[[REG:.*]],{{.*}},15
+; MIPS32: li	[[REG2:.*]],-16
 ; MIPS32: and	[[REG3:.*]],[[REG]],[[REG2]]
 ; MIPS32: subu	[[REG4:.*]],sp,[[REG3]]
 ; MIPS32: lui	[[REG5:.*]],0xe000