implement the null function for the Mips32 subzero compiler

Makefile.standalone

@@ -189,6 +189,7 @@ SRCS = \
 	IceGlobalInits.cpp \
 	IceInst.cpp \
 	IceInstARM32.cpp \
+	IceInstMIPS32.cpp \
 	IceInstX8632.cpp \
 	IceIntrinsics.cpp \
 	IceLiveness.cpp \

pydir/run-pnacl-sz.py

@@ -15,14 +15,18 @@ def TargetAssemblerFlags(target):
   # TODO(stichnot): -triple=i686-nacl should be used for a
   # sandboxing test.  This means there should be an args.sandbox
   # argument that also gets passed through to pnacl-sz.
+  # TODO(reed kotler). Need to find out exactly we need to
+  # add here for Mips32.
   flags = { 'x8632': ['-triple=i686'],
-            'arm32': ['-triple=armv7a', '-mcpu=cortex-a9', '-mattr=+neon'] }
+            'arm32': ['-triple=armv7a', '-mcpu=cortex-a9', '-mattr=+neon'],
+            'mips32': ['-triple=mipsel-none-nacl' ] }
   return flags[target]
 
 
 def TargetDisassemblerFlags(target):
   flags = { 'x8632': ['-Mintel'],
-            'arm32': [] }
+            'arm32': [],
+            'mips32':[] }
   return flags[target]
 
 
@@ -73,7 +77,7 @@ def main():
                            choices=['obj', 'asm', 'iasm'],
                            help='Output file type.  Default %(default)s.')
     argparser.add_argument('--target', default='x8632', dest='target',
-                           choices=['x8632','arm32'],
+                           choices=['x8632','arm32','mips32'],
                            help='Target architecture.  Default %(default)s.')
     argparser.add_argument('--echo-cmd', required=False,
                            action='store_true',

src/IceAssemblerMIPS32.h

@@ -49,10 +49,12 @@ public:
 
   SizeT getBundleAlignLog2Bytes() const override { return 4; }
 
-  const char *getNonExecPadDirective() const override { return ".TBD"; }
+  const char *getNonExecPadDirective() const override { return ".p2alignl"; }
 
   llvm::ArrayRef<uint8_t> getNonExecBundlePadding() const override {
-    llvm::report_fatal_error("Not yet implemented.");
+    // TODO(reed kotler) . Find out what this should be.
+    static const uint8_t Padding[] = {0xE7, 0xFE, 0xDE, 0xF0};
+    return llvm::ArrayRef<uint8_t>(Padding, 4);
   }
 
   void padWithNop(intptr_t Padding) override {

src/IceInstMIPS32.cpp

+//===- subzero/src/IceInstMips32.cpp - Mips32 instruction implementation --===//
+//
+//                        The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file
+/// This file implements the InstMips32 and OperandMips32 classes,
+/// primarily the constructors and the dump()/emit() methods.
+///
+//===----------------------------------------------------------------------===//
+
+#include "IceAssemblerMIPS32.h"
+#include "IceCfg.h"
+#include "IceCfgNode.h"
+#include "IceInst.h"
+#include "IceInstMIPS32.h"
+#include "IceOperand.h"
+#include "IceRegistersMIPS32.h"
+#include "IceTargetLoweringMIPS32.h"
+
+namespace Ice {
+
+
+InstMIPS32Ret::InstMIPS32Ret(Cfg *Func, Variable *RA, Variable *Source)
+    : InstMIPS32(Func, InstMIPS32::Ret, Source ? 2 : 1, nullptr) {
+  addSource(RA);
+  if (Source)
+    addSource(Source);
+}
+
+void InstMIPS32Ret::emit(const Cfg *Func) const {
+  if (!ALLOW_DUMP)
+    return;
+  assert(getSrcSize() > 0);
+  Variable *RA = llvm::cast<Variable>(getSrc(0));
+  assert(RA->hasReg());
+  assert(RA->getRegNum() == RegMIPS32::Reg_RA);
+  Ostream &Str = Func->getContext()->getStrEmit();
+  Str << "\t"
+      << "jr $ra"
+      << "\t";
+  RA->emit(Func);
+}
+
+void InstMIPS32Ret::emitIAS(const Cfg *Func) const {
+  (void)Func;
+  llvm_unreachable("Not yet implemented");
+}
+
+void InstMIPS32Ret::dump(const Cfg *Func) const {
+  if (!ALLOW_DUMP)
+    return;
+  Ostream &Str = Func->getContext()->getStrDump();
+  Type Ty = (getSrcSize() == 1 ? IceType_void : getSrc(0)->getType());
+  Str << "ret." << Ty << " ";
+  dumpSources(Func);
+}
+}

src/IceInstMIPS32.def

@@ -15,7 +15,7 @@
 #define SUBZERO_SRC_ICEINSTMIPS32_DEF
 
 // NOTE: PC and SP are not considered isInt, to avoid register allocating.
-// TODO (reed kotler). This needs to be scrubbed and is a placeholder to get
+// TODO(reed kotler). This needs to be scrubbed and is a placeholder to get
 // the Mips skeleton in.
 //
 #define REGMIPS32_GPR_TABLE                                                    \

src/IceInstMIPS32.h

@@ -18,11 +18,64 @@
 #define SUBZERO_SRC_ICEINSTMIPS32_H
 
 #include "IceDefs.h"
+#include "IceInst.h"
+#include "IceInstMIPS32.def"
+#include "IceOperand.h"
 
 namespace Ice {
 
 class TargetMIPS32;
-// Fill this in.
+
+/// Base class for Mips instructions.
+class InstMIPS32 : public InstTarget {
+  InstMIPS32() = delete;
+  InstMIPS32(const InstMIPS32 &) = delete;
+  InstMIPS32 &operator=(const InstMIPS32 &) = delete;
+
+public:
+  enum InstKindMIPS32 { k__Start = Inst::Target, Ret };
+
+  static const char *getWidthString(Type Ty);
+
+  void dump(const Cfg *Func) const override;
+
+protected:
+  InstMIPS32(Cfg *Func, InstKindMIPS32 Kind, SizeT Maxsrcs, Variable *Dest)
+      : InstTarget(Func, static_cast<InstKind>(Kind), Maxsrcs, Dest) {}
+  ~InstMIPS32() override {}
+  static bool isClassof(const Inst *Inst, InstKindMIPS32 MyKind) {
+    return Inst->getKind() == static_cast<InstKind>(MyKind);
+  }
+};
+
+/// Ret pseudo-instruction.  This is actually a "jr" instruction with
+/// an "ra" register operand, but epilogue lowering will search for a Ret
+/// instead of a generic "jr". This instruction also takes a Source
+/// operand (for non-void returning functions) for liveness analysis, though
+/// a FakeUse before the ret would do just as well.
+/// TODO(reed kotler): This needs was take from the ARM port and needs to be
+/// scrubbed in the future.
+class InstMIPS32Ret : public InstMIPS32 {
+
+  InstMIPS32Ret() = delete;
+  InstMIPS32Ret(const InstMIPS32Ret &) = delete;
+  InstMIPS32Ret &operator=(const InstMIPS32Ret &) = delete;
+
+public:
+  static InstMIPS32Ret *create(Cfg *Func, Variable *RA,
+                               Variable *Source = nullptr) {
+    return new (Func->allocate<InstMIPS32Ret>())
+        InstMIPS32Ret(Func, RA, Source);
+  }
+  void emit(const Cfg *Func) const override;
+  void emitIAS(const Cfg *Func) const override;
+  void dump(const Cfg *Func) const override;
+  static bool classof(const Inst *Inst) { return isClassof(Inst, Ret); }
+
+private:
+  InstMIPS32Ret(Cfg *Func, Variable *RA, Variable *Source);
+  ~InstMIPS32Ret() override {}
+};
 
 } // end of namespace Ice
 

src/IceTargetLoweringMIPS32.h

@@ -76,6 +76,9 @@ public:
     (void)C;
     llvm::report_fatal_error("Not yet implemented");
   }
+  void _ret(Variable *RA, Variable *Src0 = nullptr) {
+    Context.insert(InstMIPS32Ret::create(Func, RA, Src0));
+  }
 
   void lowerArguments() override;
   void addProlog(CfgNode *Node) override;

tests_lit/llvm2ice_tests/function_aligned.ll

@@ -13,6 +13,11 @@
 ; RUN:   --disassemble --target arm32 -i %s --args -O2 --skip-unimplemented \
 ; RUN:   | %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command FileCheck --check-prefix ARM32 %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN:   --command %p2i --filetype=asm --assemble \
+; RUN:   --disassemble --target mips32 -i %s --args -O2 --skip-unimplemented \
+; RUN:   | %if --need=target_MIPS32 --need=allow_dump \
+; RUN:   --command FileCheck --check-prefix MIPS32 %s
 
 define void @foo() {
   ret void
@@ -25,6 +30,10 @@ define void @foo() {
 ; ARM32-NEXT: 4: e7fedef0 udf
 ; ARM32-NEXT: 8: e7fedef0 udf
 ; ARM32-NEXT: c: e7fedef0 udf
+; MIPS32-LABEL: foo
+; MIPS32: 4: {{.*}} jr ra
+; MIPS32-NEXT: 8: {{.*}} nop
+; MIPS32-NEXT: c: e7fedef0
 
 define void @bar() {
   ret void
@@ -33,3 +42,6 @@ define void @bar() {
 ; CHECK-NEXT: 20: {{.*}} ret
 ; ARM32-LABEL: bar
 ; ARM32-NEXT: 10: {{.*}} bx lr
+; MIPS32-LABEL: bar
+; MIPS32: 14: {{.*}} jr ra
+; MIPS32-NEXT: 18: {{.*}} nop