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swiftshader
Commit d2a46436 by Ben Clayton
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SpirvShader: Implement OpBitReverse

Bug: b/126873455 Tests: dEQP-VK.glsl.builtin.function.integer.bitfieldreverse.* Change-Id: I8c6b73be89c24de371806f6c5d6afbf52f7161c9 Reviewed-on: https://swiftshader-review.googlesource.com/c/SwiftShader/+/28472Tested-by: 's avatarBen Clayton <bclayton@google.com> Reviewed-by: 's avatarChris Forbes <chrisforbes@google.com> Reviewed-by: 's avatarNicolas Capens <nicolascapens@google.com> Presubmit-Ready: Ben Clayton <bclayton@google.com> Kokoro-Presubmit: kokoro <noreply+kokoro@google.com>
parent 1eb017d8
Showing with 17 additions and 0 deletions
src/Pipeline/SpirvShader.cpp
......@@ -366,6 +366,7 @@ namespace sw
case spv::OpVectorExtractDynamic:
case spv::OpVectorInsertDynamic:
case spv::OpNot: // Unary ops
case spv::OpBitReverse:
case spv::OpBitCount:
case spv::OpSNegate:
case spv::OpFNegate:
......@@ -1633,6 +1634,7 @@ namespace sw
return EmitTranspose(insn, state);
case spv::OpNot:
case spv::OpBitReverse:
case spv::OpBitCount:
case spv::OpSNegate:
case spv::OpFNegate:
......@@ -2333,6 +2335,21 @@ namespace sw
case spv::OpLogicalNot: // logical not == bitwise not due to all-bits boolean representation
dst.move(i, ~src.UInt(i));
break;
case spv::OpBitReverse:
{
// TODO: Add an intrinsic to reactor. Even if there isn't a
// single vector instruction, there may be target-dependent
// ways to make this faster.
// https://graphics.stanford.edu/~seander/bithacks.html#ReverseParallel
SIMD::UInt v = src.UInt(i);
v = ((v >> 1) & SIMD::UInt(0x55555555)) | ((v & SIMD::UInt(0x55555555)) << 1);
v = ((v >> 2) & SIMD::UInt(0x33333333)) | ((v & SIMD::UInt(0x33333333)) << 2);
v = ((v >> 4) & SIMD::UInt(0x0F0F0F0F)) | ((v & SIMD::UInt(0x0F0F0F0F)) << 4);
v = ((v >> 8) & SIMD::UInt(0x00FF00FF)) | ((v & SIMD::UInt(0x00FF00FF)) << 8);
v = (v >> 16) | (v << 16);
dst.move(i, v);
break;
}
case spv::OpBitCount:
{
// TODO: Add an intrinsic to reactor. Even if there isn't a
......
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