Add DMB instruction to the ARM integrated assembler.

src/IceAssemblerARM32.cpp

@@ -45,6 +45,10 @@ static constexpr IValueT B12 = 1 << 12;
 static constexpr IValueT B13 = 1 << 13;
 static constexpr IValueT B14 = 1 << 14;
 static constexpr IValueT B15 = 1 << 15;
+static constexpr IValueT B16 = 1 << 16;
+static constexpr IValueT B17 = 1 << 17;
+static constexpr IValueT B18 = 1 << 18;
+static constexpr IValueT B19 = 1 << 19;
 static constexpr IValueT B20 = 1 << 20;
 static constexpr IValueT B21 = 1 << 21;
 static constexpr IValueT B22 = 1 << 22;
@@ -1088,6 +1092,20 @@ void AssemblerARM32::cmp(const Operand *OpRn, const Operand *OpSrc1,
   emitCompareOp(Cond, CmpOpcode, OpRn, OpSrc1, CmpName);
 }
 
+void AssemblerARM32::dmb(IValueT Option) {
+  // DMB - ARM section A8.8.43, encoding A1:
+  //   dmb <option>
+  //
+  // 1111010101111111111100000101xxxx where xxxx=Option.
+  assert(Utils::IsUint(4, Option) && "Bad dmb option");
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  const IValueT Encoding =
+      (encodeCondition(CondARM32::kNone) << kConditionShift) | B26 | B24 | B22 |
+      B21 | B20 | B19 | B18 | B17 | B16 | B15 | B14 | B13 | B12 | B6 | B4 |
+      Option;
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::eor(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {

src/IceAssemblerARM32.h

@@ -209,6 +209,8 @@ public:
 
   void cmp(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
 
+  void dmb(IValueT Option); // Option is a 4-bit value.
+
   void eor(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 

src/IceInstARM32.cpp

@@ -1763,6 +1763,15 @@ void InstARM32Dmb::emit(const Cfg *Func) const {
          "sy";
 }
 
+void InstARM32Dmb::emitIAS(const Cfg *Func) const {
+  assert(getSrcSize() == 0);
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  constexpr ARM32::IValueT SyOption = 0xF; // i.e. 1111
+  Asm->dmb(SyOption);
+  if (Asm->needsTextFixup())
+    emitUsingTextFixup(Func);
+}
+
 void InstARM32Dmb::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;

src/IceInstARM32.h

@@ -1360,6 +1360,7 @@ public:
     return new (Func->allocate<InstARM32Dmb>()) InstARM32Dmb(Func);
   }
   void emit(const Cfg *Func) const override;
+  void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Dmb); }
 

tests_lit/assembler/arm32/dmb.ll

+; Show that we know how to encode the dmb instruction.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -Om1 | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -Om1 | FileCheck %s --check-prefix=DIS
+
+declare i8 @llvm.nacl.atomic.load.i8(i8*, i32)
+
+define internal i32 @test_atomic_load_8(i32 %iptr) {
+; ASM-LABEL:test_atomic_load_8:
+; DIS-LABEL:00000000 <test_atomic_load_8>:
+; IASM-LABEL:test_atomic_load_8:
+
+entry:
+; ASM-NEXT:.Ltest_atomic_load_8$entry:
+; IASM-NEXT:.Ltest_atomic_load_8$entry:
+
+; ASM-NEXT:	sub	sp, sp, #12
+; DIS-NEXT:   0:	e24dd00c
+; IASM-NEXT:	.byte 0xc
+; IASM-NEXT:	.byte 0xd0
+; IASM-NEXT:	.byte 0x4d
+; IASM-NEXT:	.byte 0xe2
+
+; ASM-NEXT:	str	r0, [sp, #8]
+; ASM-NEXT:	# [sp, #8] = def.pseudo 
+; DIS-NEXT:   4:	e58d0008
+; IASM-NEXT:	.byte 0x8
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x8d
+; IASM-NEXT:	.byte 0xe5
+
+  %ptr = inttoptr i32 %iptr to i8*
+  ; parameter value "6" is for the sequential consistency memory order.
+  %i = call i8 @llvm.nacl.atomic.load.i8(i8* %ptr, i32 6)
+
+; ASM-NEXT:	ldr	r0, [sp, #8]
+; DIS-NEXT:   8:	e59d0008
+; IASM-NEXT:	.byte 0x8
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x9d
+; IASM-NEXT:	.byte 0xe5
+
+; ASM-NEXT:	ldrb	r0, [r0]
+; DIS-NEXT:   c:	e5d00000
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0x0
+; IASM-NEXT:	.byte 0xd0
+; IASM-NEXT:	.byte 0xe5
+
+; ASM-NEXT:	dmb	sy
+; DIS-NEXT:  10:	f57ff05f
+; IASM-NEXT:	.byte 0x5f
+; IASM-NEXT:	.byte 0xf0
+; IASM-NEXT:	.byte 0x7f
+; IASM-NEXT:	.byte 0xf5
+
+  %r = zext i8 %i to i32
+  ret i32 %r
+}