Commit d8777b0d by John Porto

Subzero. ARM32. Adds header to auto-generated register def file.

parent 718118dd
...@@ -53,6 +53,9 @@ class RegFeatures(object): ...@@ -53,6 +53,9 @@ class RegFeatures(object):
return any(self.FeaturesDict[FpFeature] for FpFeature in ( return any(self.FeaturesDict[FpFeature] for FpFeature in (
'IsFP32', 'IsFP64', 'IsVec128')) 'IsFP32', 'IsFP64', 'IsVec128'))
def DefiningXMacro(self):
return 'define X({parameters})'.format(parameters=', '.join(self.Features))
class Reg(object): class Reg(object):
def __init__(self, Name, Encode, AsmStr=None, **Features): def __init__(self, Name, Encode, AsmStr=None, **Features):
self.Name = Name self.Name = Name
...@@ -68,6 +71,9 @@ class Reg(object): ...@@ -68,6 +71,9 @@ class Reg(object):
def IsAnAliasOf(self, Other): def IsAnAliasOf(self, Other):
return Other.Name in self.Features.Aliases().Aliases return Other.Name in self.Features.Aliases().Aliases
def DefiningXMacro(self):
return self.Features.DefiningXMacro()
# Note: The following tables break the usual 80-col on purpose -- it is easier # Note: The following tables break the usual 80-col on purpose -- it is easier
# to read the register tables if each register entry is contained on a single # to read the register tables if each register entry is contained on a single
# line. # line.
...@@ -214,8 +220,9 @@ print ("// This file was auto generated by the {script} script.\n" ...@@ -214,8 +220,9 @@ print ("// This file was auto generated by the {script} script.\n"
"\n" "\n"
"#ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF\n" "#ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF\n"
"#define SUBZERO_SRC_ICEREGISTERSARM32_DEF\n".format(script=os.path.basename(sys.argv[0]))) "#define SUBZERO_SRC_ICEREGISTERSARM32_DEF\n".format(script=os.path.basename(sys.argv[0])))
for Name, RegClass in RegClasses: for Name, RegClass in RegClasses:
print '\n//{xmacro}'.format(xmacro=Reg.DefiningXMacro())
print "#define REGARM32_%s_TABLE" % Name, print "#define REGARM32_%s_TABLE" % Name,
for Reg in RegClass: for Reg in RegClass:
print '\\\n X({Reg})'.format(Reg=Reg), print '\\\n X({Reg})'.format(Reg=Reg),
......
...@@ -4,6 +4,8 @@ ...@@ -4,6 +4,8 @@
#ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF #ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF
#define SUBZERO_SRC_ICEREGISTERSARM32_DEF #define SUBZERO_SRC_ICEREGISTERSARM32_DEF
//define X(AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
#define REGARM32_GPR_TABLE \ #define REGARM32_GPR_TABLE \
X(Reg_r0, 0, "r0", 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r0, r0r1)) \ X(Reg_r0, 0, "r0", 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r0, r0r1)) \
X(Reg_r1, 1, "r1", 2, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r1, r0r1)) \ X(Reg_r1, 1, "r1", 2, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r1, r0r1)) \
...@@ -22,6 +24,8 @@ ...@@ -22,6 +24,8 @@
X(Reg_lr, 14, "lr", 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, lr)) \ X(Reg_lr, 14, "lr", 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, lr)) \
X(Reg_pc, 15, "pc", 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, pc)) X(Reg_pc, 15, "pc", 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, pc))
//define X(AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
#define REGARM32_I64PAIR_TABLE \ #define REGARM32_I64PAIR_TABLE \
X(Reg_r0r1, 0, "r0, r1", 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r0r1, r0, r1)) \ X(Reg_r0r1, 0, "r0, r1", 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r0r1, r0, r1)) \
X(Reg_r2r3, 2, "r2, r3", 2, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r2r3, r2, r3)) \ X(Reg_r2r3, 2, "r2, r3", 2, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r2r3, r2, r3)) \
...@@ -30,6 +34,8 @@ ...@@ -30,6 +34,8 @@
X(Reg_r8r9, 8, "r8, r9", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r8r9, r8, r9)) \ X(Reg_r8r9, 8, "r8, r9", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r8r9, r8, r9)) \
X(Reg_r10fp, 10, "r10, fp", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r10fp, r10, fp)) X(Reg_r10fp, 10, "r10, fp", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r10fp, r10, fp))
//define X(AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
#define REGARM32_FP32_TABLE \ #define REGARM32_FP32_TABLE \
X(Reg_s0, 0, "s0", 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s0, d0, q0)) \ X(Reg_s0, 0, "s0", 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s0, d0, q0)) \
X(Reg_s1, 1, "s1", 2, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s1, d0, q0)) \ X(Reg_s1, 1, "s1", 2, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s1, d0, q0)) \
...@@ -64,6 +70,8 @@ ...@@ -64,6 +70,8 @@
X(Reg_s30, 30, "s30", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s30, d15, q7)) \ X(Reg_s30, 30, "s30", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s30, d15, q7)) \
X(Reg_s31, 31, "s31", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s31, d15, q7)) X(Reg_s31, 31, "s31", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s31, d15, q7))
//define X(AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
#define REGARM32_FP64_TABLE \ #define REGARM32_FP64_TABLE \
X(Reg_d31, 31, "d31", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d31, q15)) \ X(Reg_d31, 31, "d31", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d31, q15)) \
X(Reg_d30, 30, "d30", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d30, q15)) \ X(Reg_d30, 30, "d30", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d30, q15)) \
...@@ -98,6 +106,8 @@ ...@@ -98,6 +106,8 @@
X(Reg_d1, 1, "d1", 2, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d1, q0, s2, s3)) \ X(Reg_d1, 1, "d1", 2, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d1, q0, s2, s3)) \
X(Reg_d0, 0, "d0", 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d0, q0, s0, s1)) X(Reg_d0, 0, "d0", 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d0, q0, s0, s1))
//define X(AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
#define REGARM32_VEC128_TABLE \ #define REGARM32_VEC128_TABLE \
X(Reg_q15, 15, "q15", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q15, d30, d31)) \ X(Reg_q15, 15, "q15", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q15, d30, d31)) \
X(Reg_q14, 14, "q14", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q14, d28, d29)) \ X(Reg_q14, 14, "q14", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q14, d28, d29)) \
......
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