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swiftshader
Commit dff7dbdb by John Porto
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Subzero. ARM32. Adds an IsGPR attribute to the register tables.

BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076 R=kschimpf@google.com Review URL: https://codereview.chromium.org/1554203002 .
parent 4a56686b
Showing with 40 additions and 39 deletions
pydir/gen_arm32_reg_tables.py
...@@ -16,16 +16,17 @@ def _ArgumentNames(Method): ...@@ -16,16 +16,17 @@ def _ArgumentNames(Method):
class RegFeatures(object): class RegFeatures(object):
def __init__(self, AsmStr=None, CCArg=0, IsScratch=0, IsPreserved=0, def __init__(self, AsmStr=None, CCArg=0, IsScratch=0, IsPreserved=0,
IsStackPtr=0, IsFramePtr=0, IsInt=0, IsI64Pair=0, IsFP32=0, IsStackPtr=0, IsFramePtr=0, IsGPR=0, IsInt=0, IsI64Pair=0,
IsFP64=0, IsVec128=0, Aliases=None): IsFP32=0, IsFP64=0, IsVec128=0, Aliases=None):
assert (not IsInt) or IsGPR
assert (not IsI64Pair) or (not IsGPR)
assert not (IsInt and IsI64Pair) assert not (IsInt and IsI64Pair)
assert not (IsFP32 and IsFP64) assert not (IsFP32 and IsFP64)
assert not (IsFP32 and IsVec128) assert not (IsFP32 and IsVec128)
assert not (IsFP64 and IsVec128) assert not (IsFP64 and IsVec128)
assert not ((IsInt or IsI64Pair) and (IsFP32 or IsFP64 or IsVec128)) assert not ((IsGPR) and (IsFP32 or IsFP64 or IsVec128))
assert (not IsFramePtr) or IsInt assert (not IsFramePtr) or IsGPR
assert (not IsStackPtr) or not( assert (not IsStackPtr) or IsGPR
IsInt or IsI64Pair or IsFP32 or IsFP64 or IsVec128)
assert not (IsScratch and IsPreserved) assert not (IsScratch and IsPreserved)
self.Features = [x for x in _ArgumentNames(self.__init__)] self.Features = [x for x in _ArgumentNames(self.__init__)]
self.FeaturesDict = {} self.FeaturesDict = {}
...@@ -71,22 +72,22 @@ class Reg(object): ...@@ -71,22 +72,22 @@ class Reg(object):
# to read the register tables if each register entry is contained on a single # to read the register tables if each register entry is contained on a single
# line. # line.
GPRs = [ GPRs = [
Reg( 'r0', 0, IsScratch=1, CCArg=1, IsInt=1, Aliases= 'r0, r0r1'), Reg( 'r0', 0, IsScratch=1, CCArg=1, IsGPR = 1, IsInt=1, Aliases= 'r0, r0r1'),
Reg( 'r1', 1, IsScratch=1, CCArg=2, IsInt=1, Aliases= 'r1, r0r1'), Reg( 'r1', 1, IsScratch=1, CCArg=2, IsGPR = 1, IsInt=1, Aliases= 'r1, r0r1'),
Reg( 'r2', 2, IsScratch=1, CCArg=3, IsInt=1, Aliases= 'r2, r2r3'), Reg( 'r2', 2, IsScratch=1, CCArg=3, IsGPR = 1, IsInt=1, Aliases= 'r2, r2r3'),
Reg( 'r3', 3, IsScratch=1, CCArg=4, IsInt=1, Aliases= 'r3, r2r3'), Reg( 'r3', 3, IsScratch=1, CCArg=4, IsGPR = 1, IsInt=1, Aliases= 'r3, r2r3'),
Reg( 'r4', 4, IsPreserved=1, IsInt=1, Aliases= 'r4, r4r5'), Reg( 'r4', 4, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r4, r4r5'),
Reg( 'r5', 5, IsPreserved=1, IsInt=1, Aliases= 'r5, r4r5'), Reg( 'r5', 5, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r5, r4r5'),
Reg( 'r6', 6, IsPreserved=1, IsInt=1, Aliases= 'r6, r6r7'), Reg( 'r6', 6, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r6, r6r7'),
Reg( 'r7', 7, IsPreserved=1, IsInt=1, Aliases= 'r7, r6r7'), Reg( 'r7', 7, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r7, r6r7'),
Reg( 'r8', 8, IsPreserved=1, IsInt=1, Aliases= 'r8, r8r9'), Reg( 'r8', 8, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r8, r8r9'),
Reg( 'r9', 9, IsPreserved=1, IsInt=0, Aliases= 'r9, r8r9'), Reg( 'r9', 9, IsPreserved=1, IsGPR = 1, IsInt=0, Aliases= 'r9, r8r9'),
Reg('r10', 10, IsPreserved=1, IsInt=1, Aliases='r10, r10fp'), Reg('r10', 10, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases='r10, r10fp'),
Reg( 'fp', 11, IsPreserved=1, IsInt=1, IsFramePtr=1, Aliases= 'fp, r10fp'), Reg( 'fp', 11, IsPreserved=1, IsGPR = 1, IsInt=1, IsFramePtr=1, Aliases= 'fp, r10fp'),
Reg( 'ip', 12, IsScratch=1, IsInt=0, Aliases= 'ip'), Reg( 'ip', 12, IsScratch=1, IsGPR = 1, IsInt=0, Aliases= 'ip'),
Reg( 'sp', 13, IsScratch=0, IsInt=0, IsStackPtr=1, Aliases= 'sp'), Reg( 'sp', 13, IsScratch=0, IsGPR = 1, IsInt=0, IsStackPtr=1, Aliases= 'sp'),
Reg( 'lr', 14, IsScratch=0, IsInt=0, Aliases= 'lr'), Reg( 'lr', 14, IsScratch=0, IsGPR = 1, IsInt=0, Aliases= 'lr'),
Reg( 'pc', 15, IsScratch=0, IsInt=0, Aliases= 'pc'), Reg( 'pc', 15, IsScratch=0, IsGPR = 1, IsInt=0, Aliases= 'pc'),
] ]
I64Pairs = [ I64Pairs = [
......
src/IceInstARM32.def
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
#include "IceRegistersARM32.def" #include "IceRegistersARM32.def"
// The register tables defined in IceRegistersARM32 use the following x-macro: // The register tables defined in IceRegistersARM32 use the following x-macro:
//#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, //#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,
// isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) // isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
// We also provide a combined table, so that there is a namespace where all of // We also provide a combined table, so that there is a namespace where all of
// the registers are considered and have distinct numberings. This is in // the registers are considered and have distinct numberings. This is in
...@@ -43,14 +43,14 @@ ...@@ -43,14 +43,14 @@
// numbers will be encoded in binaries and values can overlap. // numbers will be encoded in binaries and values can overlap.
#define REGARM32_TABLE \ #define REGARM32_TABLE \
/* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ /* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \ isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \
REGARM32_GPR_TABLE \ REGARM32_GPR_TABLE \
REGARM32_I64PAIR_TABLE \ REGARM32_I64PAIR_TABLE \
REGARM32_FP32_TABLE \ REGARM32_FP32_TABLE \
REGARM32_FP64_TABLE \ REGARM32_FP64_TABLE \
REGARM32_VEC128_TABLE REGARM32_VEC128_TABLE
//#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, //#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,
// isInt, isFP32, isFP64, isVec128, alias_init) // isGPR, isInt, isFP32, isFP64, isVec128, alias_init)
#define REGARM32_TABLE_BOUNDS \ #define REGARM32_TABLE_BOUNDS \
/* val, init */ \ /* val, init */ \
......
src/IceRegistersARM32.h
...@@ -29,7 +29,7 @@ public: ...@@ -29,7 +29,7 @@ public:
/// to binary encode register operands in instructions. /// to binary encode register operands in instructions.
enum AllRegisters { enum AllRegisters {
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
val, val,
REGARM32_TABLE REGARM32_TABLE
#undef X #undef X
...@@ -43,7 +43,7 @@ public: ...@@ -43,7 +43,7 @@ public:
/// binary encode register operands in instructions. /// binary encode register operands in instructions.
enum GPRRegister { enum GPRRegister {
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
Encoded_##val = encode, Encoded_##val = encode,
REGARM32_GPR_TABLE REGARM32_GPR_TABLE
#undef X #undef X
...@@ -54,7 +54,7 @@ public: ...@@ -54,7 +54,7 @@ public:
/// to binary encode register operands in instructions. /// to binary encode register operands in instructions.
enum SRegister { enum SRegister {
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
Encoded_##val = encode, Encoded_##val = encode,
REGARM32_FP32_TABLE REGARM32_FP32_TABLE
#undef X #undef X
...@@ -65,7 +65,7 @@ public: ...@@ -65,7 +65,7 @@ public:
/// to binary encode register operands in instructions. /// to binary encode register operands in instructions.
enum DRegister { enum DRegister {
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
Encoded_##val = encode, Encoded_##val = encode,
REGARM32_FP64_TABLE REGARM32_FP64_TABLE
#undef X #undef X
...@@ -76,7 +76,7 @@ public: ...@@ -76,7 +76,7 @@ public:
/// used to binary encode register operands in instructions. /// used to binary encode register operands in instructions.
enum QRegister { enum QRegister {
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
Encoded_##val = encode, Encoded_##val = encode,
REGARM32_VEC128_TABLE REGARM32_VEC128_TABLE
#undef X #undef X
......
src/IceTargetLoweringARM32.cpp
...@@ -182,7 +182,7 @@ TargetARM32Features::TargetARM32Features(const ClFlags &Flags) { ...@@ -182,7 +182,7 @@ TargetARM32Features::TargetARM32Features(const ClFlags &Flags) {
namespace { namespace {
constexpr SizeT NumGPRArgs = constexpr SizeT NumGPRArgs =
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
+(((cc_arg) > 0) ? 1 : 0) +(((cc_arg) > 0) ? 1 : 0)
REGARM32_GPR_TABLE REGARM32_GPR_TABLE
#undef X #undef X
...@@ -191,7 +191,7 @@ std::array<uint32_t, NumGPRArgs> GPRArgInitializer; ...@@ -191,7 +191,7 @@ std::array<uint32_t, NumGPRArgs> GPRArgInitializer;
constexpr SizeT NumI64Args = constexpr SizeT NumI64Args =
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
+(((cc_arg) > 0) ? 1 : 0) +(((cc_arg) > 0) ? 1 : 0)
REGARM32_I64PAIR_TABLE REGARM32_I64PAIR_TABLE
#undef X #undef X
...@@ -200,7 +200,7 @@ std::array<uint32_t, NumI64Args> I64ArgInitializer; ...@@ -200,7 +200,7 @@ std::array<uint32_t, NumI64Args> I64ArgInitializer;
constexpr SizeT NumFP32Args = constexpr SizeT NumFP32Args =
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
+(((cc_arg) > 0) ? 1 : 0) +(((cc_arg) > 0) ? 1 : 0)
REGARM32_FP32_TABLE REGARM32_FP32_TABLE
#undef X #undef X
...@@ -209,7 +209,7 @@ std::array<uint32_t, NumFP32Args> FP32ArgInitializer; ...@@ -209,7 +209,7 @@ std::array<uint32_t, NumFP32Args> FP32ArgInitializer;
constexpr SizeT NumFP64Args = constexpr SizeT NumFP64Args =
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
+(((cc_arg) > 0) ? 1 : 0) +(((cc_arg) > 0) ? 1 : 0)
REGARM32_FP64_TABLE REGARM32_FP64_TABLE
#undef X #undef X
...@@ -218,7 +218,7 @@ std::array<uint32_t, NumFP64Args> FP64ArgInitializer; ...@@ -218,7 +218,7 @@ std::array<uint32_t, NumFP64Args> FP64ArgInitializer;
constexpr SizeT NumVec128Args = constexpr SizeT NumVec128Args =
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
+(((cc_arg > 0)) ? 1 : 0) +(((cc_arg > 0)) ? 1 : 0)
REGARM32_VEC128_TABLE REGARM32_VEC128_TABLE
#undef X #undef X
...@@ -240,7 +240,7 @@ void TargetARM32::staticInit() { ...@@ -240,7 +240,7 @@ void TargetARM32::staticInit() {
llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM); llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM);
ScratchRegs.resize(RegARM32::Reg_NUM); ScratchRegs.resize(RegARM32::Reg_NUM);
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
IntegerRegisters[RegARM32::val] = isInt; \ IntegerRegisters[RegARM32::val] = isInt; \
I64PairRegisters[RegARM32::val] = isI64Pair; \ I64PairRegisters[RegARM32::val] = isI64Pair; \
Float32Registers[RegARM32::val] = isFP32; \ Float32Registers[RegARM32::val] = isFP32; \
...@@ -829,7 +829,7 @@ bool TargetARM32::doBranchOpt(Inst *I, const CfgNode *NextNode) { ...@@ -829,7 +829,7 @@ bool TargetARM32::doBranchOpt(Inst *I, const CfgNode *NextNode) {
const char *RegARM32::RegNames[] = { const char *RegARM32::RegNames[] = {
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
name, name,
REGARM32_TABLE REGARM32_TABLE
#undef X #undef X
...@@ -844,7 +844,7 @@ IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const { ...@@ -844,7 +844,7 @@ IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const {
Variable *TargetARM32::getPhysicalRegister(SizeT RegNum, Type Ty) { Variable *TargetARM32::getPhysicalRegister(SizeT RegNum, Type Ty) {
static const Type DefaultType[] = { static const Type DefaultType[] = {
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
(isFP32) \ (isFP32) \
? IceType_f32 \ ? IceType_f32 \
: ((isFP64) ? IceType_f64 : ((isVec128 ? IceType_v4i32 : IceType_i32))), : ((isFP64) ? IceType_f64 : ((isVec128 ? IceType_v4i32 : IceType_i32))),
...@@ -1835,7 +1835,7 @@ llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include, ...@@ -1835,7 +1835,7 @@ llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include,
llvm::SmallBitVector Registers(RegARM32::Reg_NUM); llvm::SmallBitVector Registers(RegARM32::Reg_NUM);
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \ #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \ isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
if (scratch && (Include & RegSet_CallerSave)) \ if (scratch && (Include & RegSet_CallerSave)) \
Registers[RegARM32::val] = true; \ Registers[RegARM32::val] = true; \
if (preserved && (Include & RegSet_CalleeSave)) \ if (preserved && (Include & RegSet_CalleeSave)) \
......
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