Subzero. ARM32. Vector lowering. Subtract.

src/IceInstARM32.cpp

@@ -674,16 +674,17 @@ template <> void InstARM32Vsub::emitIAS(const Cfg *Func) const {
   switch (Dest->getType()) {
   default:
     // TODO(kschimpf) Figure if more cases are needed.
-    Asm->setNeedsTextFixup();
+    emitUsingTextFixup(Func);
     break;
   case IceType_f32:
     Asm->vsubs(getDest(), getSrc(0), getSrc(1), CondARM32::AL);
+    assert(!Asm->needsTextFixup());
     break;
   case IceType_f64:
     Asm->vsubd(getDest(), getSrc(0), getSrc(1), CondARM32::AL);
+    assert(!Asm->needsTextFixup());
     break;
   }
-  assert(!Asm->needsTextFixup());
 }
 
 template <> void InstARM32Vmul::emitIAS(const Cfg *Func) const {

src/IceTargetLoweringARM32.cpp

@@ -2805,6 +2805,8 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Instr) {
     // Explicitly whitelist vector instructions we have implemented/enabled.
     case InstArithmetic::Fadd:
     case InstArithmetic::Add:
+    case InstArithmetic::Fsub:
+    case InstArithmetic::Sub:
       break;
     }
   }
@@ -2974,6 +2976,7 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Instr) {
   }
   case InstArithmetic::Sub: {
     if (const Inst *Src1Producer = Computations.getProducerOf(Src1)) {
+      assert(!isVectorType(DestTy));
       Variable *Src0R = legalizeToReg(Src0);
       Variable *Src1R = legalizeToReg(Src1Producer->getSrc(0));
       Variable *Src2R = legalizeToReg(Src1Producer->getSrc(1));
@@ -2983,6 +2986,7 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Instr) {
     }
 
     if (Srcs.hasConstOperand()) {
+      assert(!isVectorType(DestTy));
       if (Srcs.immediateIsFlexEncodable()) {
         Variable *Src0R = Srcs.src0R(this);
         Operand *Src1RF = Srcs.src1RF(this);
@@ -3004,7 +3008,11 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Instr) {
     }
     Variable *Src0R = Srcs.unswappedSrc0R(this);
     Variable *Src1R = Srcs.unswappedSrc1R(this);
-    _sub(T, Src0R, Src1R);
+    if (isVectorType(DestTy)) {
+      _vsub(T, Src0R, Src1R);
+    } else {
+      _sub(T, Src0R, Src1R);
+    }
     _mov(Dest, T);
     return;
   }

tests_lit/assembler/arm32/sub-vec.ll

+; Show that we know how to translate vsub vector instructions.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
+; RUN:   -reg-use q10,q11 \
+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 \
+; RUN:   -reg-use q10,q11 \
+; RUN:   | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
+; RUN:   -reg-use q10,q11 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 \
+; RUN:   -reg-use q10,q11 \
+; RUN:   | FileCheck %s --check-prefix=DIS
+
+define internal <4 x float> @testVsubFloat4(<4 x float> %v1, <4 x float> %v2) {
+; ASM-LABEL: testVsubFloat4:
+; DIS-LABEL: 00000000 <testVsubFloat4>:
+; IASM-LABEL: testVsubFloat4:
+
+entry:
+  %res = fsub <4 x float> %v1, %v2
+
+; ASM:     vsub.f32        q10, q10, q11
+; DIS:   8:       f2644de6
+; IASM:     vsub.f32
+
+  ret <4 x float> %res
+}
+
+define internal <4 x i32> @testVsub4i32(<4 x i32> %v1, <4 x i32> %v2) {
+; ASM-LABEL: testVsub4i32:
+; DIS-LABEL: 00000020 <testVsub4i32>:
+; IASM-LABEL: testVsub4i32:
+
+entry:
+  %res = sub <4 x i32> %v1, %v2
+
+; ASM:     vsub.i32        q10, q10, q11
+; DIS:   28:       f36448e6
+; IASM:     vsub.i32
+
+  ret <4 x i32> %res
+}
+
+define internal <8 x i16> @testVsub8i16(<8 x i16> %v1, <8 x i16> %v2) {
+; ASM-LABEL: testVsub8i16:
+; DIS-LABEL: 00000040 <testVsub8i16>:
+; IASM-LABEL: testVsub8i16:
+
+entry:
+  %res = sub <8 x i16> %v1, %v2
+
+; ASM:     vsub.i16        q10, q10, q11
+; DIS:   48:       f35448e6
+; IASM:     vsub.i16
+
+  ret <8 x i16> %res
+}
+
+define internal <16 x i8> @testVsub16i8(<16 x i8> %v1, <16 x i8> %v2) {
+; ASM-LABEL: testVsub16i8:
+; DIS-LABEL: 00000060 <testVsub16i8>:
+; IASM-LABEL: testVsub16i8:
+
+entry:
+  %res = sub <16 x i8> %v1, %v2
+
+; ASM:     vsub.i8        q10, q10, q11
+; DIS:   68:       f34448e6
+; IASM:     vsub.i8
+
+  ret <16 x i8> %res
+}

tests_lit/assembler/arm32/vldr-vector.ll

@@ -45,3 +45,29 @@ entry:
 
   ret <4 x i32> %ret
 }
+
+define internal <8 x i16> @testDeref8i16(<8 x i16> *%p) {
+; ASM-LABEL: testDeref8i16:
+; DIS-LABEL: 00000020 <testDeref8i16>:
+; IASM-LABEL: testDeref8i16:
+
+entry:
+  %ret = load <8 x i16>, <8 x i16>* %p, align 2
+; ASM:     vld1.64	q0, [r0]
+; DIS:   20:       f4200acf
+
+  ret <8 x i16> %ret
+}
+
+define internal <16 x i8> @testDeref16i8(<16 x i8> *%p) {
+; ASM-LABEL: testDeref16i8:
+; DIS-LABEL: 00000030 <testDeref16i8>:
+; IASM-LABEL: testDeref16i8:
+
+entry:
+  %ret = load <16 x i8>, <16 x i8>* %p, align 1
+; ASM:     vld1.64	q0, [r0]
+; DIS:   30:       f4200acf
+
+  ret <16 x i8> %ret
+}