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swiftshader
Commit ed2c06b2 by John Porto
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Subzero. Adds I64 register pairs for ARM32.

This is in preparation for llvm.nacl.atomic.* lowerings. atomic i64 loads and stores require their operands to be consecutive registers starting at an even register that is not r14. BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076 R=kschimpf@google.com Review URL: https://codereview.chromium.org/1382063002 .
parent 7cb12682
Showing with 22 additions and 10 deletions
src/IceRegistersARM32.h
......@@ -27,7 +27,7 @@ public:
/// to binary encode register operands in instructions.
enum AllRegisters {
#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
isFP32, isFP64, isVec128, alias_init) \
isI64Pair, isFP32, isFP64, isVec128, alias_init) \
val,
REGARM32_TABLE
#undef X
......@@ -41,7 +41,7 @@ public:
/// binary encode register operands in instructions.
enum GPRRegister {
#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
isFP32, isFP64, isVec128, alias_init) \
isI64Pair, isFP32, isFP64, isVec128, alias_init) \
Encoded_##val = encode,
REGARM32_GPR_TABLE
#undef X
......@@ -52,7 +52,7 @@ public:
/// to binary encode register operands in instructions.
enum SRegister {
#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
isFP32, isFP64, isVec128, alias_init) \
isI64Pair, isFP32, isFP64, isVec128, alias_init) \
Encoded_##val = encode,
REGARM32_FP32_TABLE
#undef X
......@@ -63,7 +63,7 @@ public:
/// to binary encode register operands in instructions.
enum DRegister {
#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
isFP32, isFP64, isVec128, alias_init) \
isI64Pair, isFP32, isFP64, isVec128, alias_init) \
Encoded_##val = encode,
REGARM32_FP64_TABLE
#undef X
......@@ -74,7 +74,7 @@ public:
/// used to binary encode register operands in instructions.
enum QRegister {
#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
isFP32, isFP64, isVec128, alias_init) \
isI64Pair, isFP32, isFP64, isVec128, alias_init) \
Encoded_##val = encode,
REGARM32_VEC128_TABLE
#undef X
......@@ -87,6 +87,16 @@ public:
return GPRRegister(RegNum - Reg_GPR_First);
}
static inline GPRRegister getI64PairFirstGPRNum(int32_t RegNum) {
assert(Reg_I64PAIR_First <= RegNum);
assert(RegNum <= Reg_I64PAIR_Last);
return GPRRegister(2 * (RegNum - Reg_I64PAIR_First + Reg_GPR_First));
}
static inline bool isI64RegisterPair(int32_t RegNum) {
return Reg_I64PAIR_First <= RegNum && RegNum <= Reg_I64PAIR_Last;
}
static inline SRegister getEncodedSReg(int32_t RegNum) {
assert(Reg_SREG_First <= RegNum);
assert(RegNum <= Reg_SREG_Last);
......
src/IceTargetLoweringARM32.cpp
......@@ -176,14 +176,16 @@ TargetARM32::TargetARM32(Cfg *Func)
// initialize in some sort of static initializer for the class.
// Limit this size (or do all bitsets need to be the same width)???
llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM);
llvm::SmallBitVector Float32Registers(RegARM32::Reg_NUM);
llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM);
llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM);
llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM);
ScratchRegs.resize(RegARM32::Reg_NUM);
#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
isFP32, isFP64, isVec128, alias_init) \
isI64Pair, isFP32, isFP64, isVec128, alias_init) \
IntegerRegisters[RegARM32::val] = isInt; \
I64PairRegisters[RegARM32::val] = isI64Pair; \
Float32Registers[RegARM32::val] = isFP32; \
Float64Registers[RegARM32::val] = isFP64; \
VectorRegisters[RegARM32::val] = isVec128; \
......@@ -203,7 +205,7 @@ TargetARM32::TargetARM32(Cfg *Func)
TypeToRegisterSet[IceType_i8] = IntegerRegisters;
TypeToRegisterSet[IceType_i16] = IntegerRegisters;
TypeToRegisterSet[IceType_i32] = IntegerRegisters;
TypeToRegisterSet[IceType_i64] = IntegerRegisters;
TypeToRegisterSet[IceType_i64] = I64PairRegisters;
TypeToRegisterSet[IceType_f32] = Float32Registers;
TypeToRegisterSet[IceType_f64] = Float64Registers;
TypeToRegisterSet[IceType_v4i1] = VectorRegisters;
......@@ -372,7 +374,7 @@ IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const {
(void)Ty;
static const char *RegNames[] = {
#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
isFP32, isFP64, isVec128, alias_init) \
isI64Pair, isFP32, isFP64, isVec128, alias_init) \
name,
REGARM32_TABLE
#undef X
......@@ -384,7 +386,7 @@ IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const {
Variable *TargetARM32::getPhysicalRegister(SizeT RegNum, Type Ty) {
static const Type DefaultType[] = {
#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
isFP32, isFP64, isVec128, alias_init) \
isI64Pair, isFP32, isFP64, isVec128, alias_init) \
(isFP32) \
? IceType_f32 \
: ((isFP64) ? IceType_f64 : ((isVec128 ? IceType_v4i32 : IceType_i32))),
......@@ -1165,7 +1167,7 @@ llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include,
llvm::SmallBitVector Registers(RegARM32::Reg_NUM);
#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
isFP32, isFP64, isVec128, alias_init) \
isI64Pair, isFP32, isFP64, isVec128, alias_init) \
if (scratch && (Include & RegSet_CallerSave)) \
Registers[RegARM32::val] = true; \
if (preserved && (Include & RegSet_CalleeSave)) \
......
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