Subzero. ARM32. Address mode formation.

src/IceInstARM32.cpp

@@ -33,7 +33,7 @@ const struct TypeARM32Attributes_ {
   int8_t SExtAddrOffsetBits;
   int8_t ZExtAddrOffsetBits;
 } TypeARM32Attributes[] = {
-#define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr)          \
+#define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr, shaddr)  \
   { int_width, vec_width, sbits, ubits }                                       \
   ,
     ICETYPEARM32_TABLE

src/IceInstARM32.def

@@ -289,23 +289,23 @@
 // extending load/stores).
 #define ICETYPEARM32_TABLE                                                     \
   /* tag,          element type, int_width, vec_width, addr bits sext, zext,   \
-     reg-reg addr allowed */                                                   \
-  X(IceType_void,  IceType_void, "" , ""    , 0 , 0 , 0)                       \
-  X(IceType_i1,    IceType_void, "b", ""    , 8 , 12, 1)                       \
-  X(IceType_i8,    IceType_void, "b", ""    , 8 , 12, 1)                       \
-  X(IceType_i16,   IceType_void, "h", ""    , 8 , 8 , 1)                       \
-  X(IceType_i32,   IceType_void, "" , ""    , 12, 12, 1)                       \
-  X(IceType_i64,   IceType_void, "d", ""    , 0 , 0 , 0)                       \
-  X(IceType_f32,   IceType_void, "" , ".f32", 8,  8 , 0)                       \
-  X(IceType_f64,   IceType_void, "" , ".f64", 8,  8 , 0)                       \
-  X(IceType_v4i1,  IceType_i32 , "" , ".i32", 0 , 0 , 1)                       \
-  X(IceType_v8i1,  IceType_i16 , "" , ".i16", 0 , 0 , 1)                       \
-  X(IceType_v16i1, IceType_i8  , "" , ".i8" , 0 , 0 , 1)                       \
-  X(IceType_v16i8, IceType_i8  , "" , ".i8" , 0 , 0 , 1)                       \
-  X(IceType_v8i16, IceType_i16 , "" , ".i16", 0 , 0 , 1)                       \
-  X(IceType_v4i32, IceType_i32 , "" , ".i32", 0 , 0 , 1)                       \
-  X(IceType_v4f32, IceType_f32 , "" , ".f32", 0 , 0 , 1)
-//#define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr)
+     reg-reg addr allowed, shift allowed, */                                   \
+  X(IceType_void,  IceType_void, "" , ""    , 0 , 0 , 0, 0)                    \
+  X(IceType_i1,    IceType_void, "b", ""    , 8 , 12, 1, 1)                    \
+  X(IceType_i8,    IceType_void, "b", ""    , 8 , 12, 1, 1)                    \
+  X(IceType_i16,   IceType_void, "h", ""    , 8 , 8 , 1, 0)                    \
+  X(IceType_i32,   IceType_void, "" , ""    , 12, 12, 1, 1)                    \
+  X(IceType_i64,   IceType_void, "d", ""    , 12, 12, 1, 1)                    \
+  X(IceType_f32,   IceType_void, "" , ".f32", 8,  8 , 0, 0)                    \
+  X(IceType_f64,   IceType_void, "" , ".f64", 8,  8 , 0, 0)                    \
+  X(IceType_v4i1,  IceType_i32 , "" , ".i32", 0 , 0 , 1, 0)                    \
+  X(IceType_v8i1,  IceType_i16 , "" , ".i16", 0 , 0 , 1, 0)                    \
+  X(IceType_v16i1, IceType_i8  , "" , ".i8" , 0 , 0 , 1, 0)                    \
+  X(IceType_v16i8, IceType_i8  , "" , ".i8" , 0 , 0 , 1, 0)                    \
+  X(IceType_v8i16, IceType_i16 , "" , ".i16", 0 , 0 , 1, 0)                    \
+  X(IceType_v4i32, IceType_i32 , "" , ".i32", 0 , 0 , 1, 0)                    \
+  X(IceType_v4f32, IceType_f32 , "" , ".f32", 0 , 0 , 1, 0)
+//#define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr, shaddr)
 
 // Shifter types for Data-processing operands as defined in section A5.1.2.
 #define ICEINSTARM32SHIFT_TABLE                                                \

src/IceTargetLoweringARM32.h

@@ -544,12 +544,23 @@ protected:
   /// If the offset is not legal, use a new base register that accounts for the
   /// offset, such that the addressing mode offset bits are now legal.
   void legalizeStackSlots();
-  /// Returns true if the given Offset can be represented in a stack ldr/str.
-  bool isLegalVariableStackOffset(Type Ty, int32_t Offset) const;
-  /// Assuming Var needs its offset legalized, define a new base register
-  /// centered on the given Var's offset plus StackAdjust, and use it.
-  StackVariable *legalizeVariableSlot(Variable *Var, int32_t StackAdjust,
-                                      Variable *OrigBaseReg);
+  /// Returns true if the given Offset can be represented in a ldr/str.
+  bool isLegalMemOffset(Type Ty, int32_t Offset) const;
+  // Creates a new Base register centered around
+  // [OrigBaseReg, +/- Offset+StackAdjust].
+  Variable *newBaseRegister(int32_t Offset, int32_t StackAdjust,
+                            Variable *OrigBaseReg);
+  /// Creates a new, legal StackVariable w.r.t. ARM's Immediate requirements.
+  /// This method is not very smart: it will always create and return a new
+  /// StackVariable, even if Offset + StackAdjust is encodable.
+  StackVariable *legalizeStackSlot(Type Ty, int32_t Offset, int32_t StackAdjust,
+                                   Variable *OrigBaseReg, Variable **NewBaseReg,
+                                   int32_t *NewBaseOffset);
+  /// Legalizes Mov if its Source (or Destination) contains an invalid
+  /// immediate.
+  void legalizeMovStackAddrImm(InstARM32Mov *Mov, int32_t StackAdjust,
+                               Variable *OrigBaseReg, Variable **NewBaseReg,
+                               int32_t *NewBaseOffset);
 
   TargetARM32Features CPUFeatures;
   bool UsesFramePointer = false;
@@ -614,8 +625,12 @@ protected:
 private:
   ~TargetARM32() override = default;
 
+  OperandARM32Mem *formAddressingMode(Type Ty, Cfg *Func, const Inst *LdSt,
+                                      Operand *Base);
+
   void lowerTruncToFlags(Operand *Src, CondARM32::Cond *CondIfTrue,
                          CondARM32::Cond *CondIfFalse);
+
   class BoolComputationTracker {
   public:
     BoolComputationTracker() = default;