Commit fb280672 by Ben Clayton

src/Vulkan: Fixup all printf-style messages

There were lots of dodgy casts, wrong specifiers, or missing specifiers. Could easily cause undefined behavior. Bug: b/127433389 Change-Id: I2859993509b897d4a7c649f87ab74d440be4590c Reviewed-on: https://swiftshader-review.googlesource.com/c/SwiftShader/+/29930 Kokoro-Presubmit: kokoro <noreply+kokoro@google.com> Tested-by: 's avatarBen Clayton <bclayton@google.com> Reviewed-by: 's avatarNicolas Capens <nicolascapens@google.com>
parent 1762c381
...@@ -2406,7 +2406,7 @@ namespace sw ...@@ -2406,7 +2406,7 @@ namespace sw
return EmitImageTexelPointer(insn, state); return EmitImageTexelPointer(insn, state);
default: default:
UNIMPLEMENTED("opcode: %s", OpcodeName(opcode).c_str()); UNIMPLEMENTED("%s", OpcodeName(opcode).c_str());
break; break;
} }
...@@ -3080,7 +3080,7 @@ namespace sw ...@@ -3080,7 +3080,7 @@ namespace sw
break; break;
} }
default: default:
UNIMPLEMENTED("Unhandled unary operator %s", OpcodeName(insn.opcode()).c_str()); UNIMPLEMENTED("%s", OpcodeName(insn.opcode()).c_str());
} }
} }
...@@ -3276,7 +3276,7 @@ namespace sw ...@@ -3276,7 +3276,7 @@ namespace sw
dst.move(i + lhsType.sizeInComponents, MulHigh(lhs.UInt(i), rhs.UInt(i))); dst.move(i + lhsType.sizeInComponents, MulHigh(lhs.UInt(i), rhs.UInt(i)));
break; break;
default: default:
UNIMPLEMENTED("Unhandled binary operator %s", OpcodeName(insn.opcode()).c_str()); UNIMPLEMENTED("%s", OpcodeName(insn.opcode()).c_str());
} }
} }
...@@ -5099,7 +5099,7 @@ namespace sw ...@@ -5099,7 +5099,7 @@ namespace sw
v = ExchangeAtomic(Pointer<UInt>(&ptr.base[offset]), laneValue, memoryOrder); v = ExchangeAtomic(Pointer<UInt>(&ptr.base[offset]), laneValue, memoryOrder);
break; break;
default: default:
UNIMPLEMENTED("Atomic op", OpcodeName(insn.opcode()).c_str()); UNIMPLEMENTED("%s", OpcodeName(insn.opcode()).c_str());
break; break;
} }
x = Insert(x, v, j); x = Insert(x, v, j);
......
...@@ -453,7 +453,7 @@ namespace rr ...@@ -453,7 +453,7 @@ namespace rr
case llvm::AtomicOrdering::AcquireRelease: return std::memory_order_acq_rel; case llvm::AtomicOrdering::AcquireRelease: return std::memory_order_acq_rel;
case llvm::AtomicOrdering::SequentiallyConsistent: return std::memory_order_seq_cst; case llvm::AtomicOrdering::SequentiallyConsistent: return std::memory_order_seq_cst;
default: default:
UNREACHABLE("memoryOrder: %d", memoryOrder); UNREACHABLE("memoryOrder: %d", int(memoryOrder));
return std::memory_order_acq_rel; return std::memory_order_acq_rel;
} }
} }
......
...@@ -171,7 +171,7 @@ std::vector<uint32_t> preprocessSpirv( ...@@ -171,7 +171,7 @@ std::vector<uint32_t> preprocessSpirv(
case SPV_MSG_INFO: category = "INFO"; break; case SPV_MSG_INFO: category = "INFO"; break;
case SPV_MSG_DEBUG: category = "DEBUG"; break; case SPV_MSG_DEBUG: category = "DEBUG"; break;
} }
vk::trace("%s: %d:%d %s", category, p.line, p.column, m); vk::trace("%s: %d:%d %s", category, int(p.line), int(p.column), m);
}); });
opt.RegisterPass(spvtools::CreateInlineExhaustivePass()); opt.RegisterPass(spvtools::CreateInlineExhaustivePass());
......
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