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swiftshader
Commit fbdc7e4c by Jim Stichnoth
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Subzero: Fix trailing whitespace errors.

To view the non-whitespace changes in this CL: git cl patch -b testbranch 1678133003 git diff -w --ignore-blank-lines -b master Such changes are only in gen_arm32_reg_tables.py and IceInst.cpp. There are lots of tab characters in .ll files that shouldn't be there, but fixing them would require some thought about how to do consistent formatting, so that's left for later. BUG= none R=eholk@chromium.org, kschimpf@google.com Review URL: https://codereview.chromium.org/1678133003 .
parent d91cbbfa
Showing with 98 additions and 117 deletions
Makefile
......@@ -28,4 +28,3 @@ else
-DALLOW_LLVM_IR_AS_INPUT=1 -DALLOW_MINIMAL_BUILD=0 \
-DPNACL_BROWSER_TRANSLATOR=0
endif
pydir/gen_arm32_reg_tables.py
......@@ -221,9 +221,9 @@ print ("// This file was auto generated by the {script} script.\n"
"#define SUBZERO_SRC_ICEREGISTERSARM32_DEF\n".format(script=os.path.basename(sys.argv[0])))
for Name, RegClass in RegClasses:
print '\n//{xmacro}'.format(xmacro=Reg.DefiningXMacro())
print '//{xmacro}'.format(xmacro=Reg.DefiningXMacro())
print "#define REGARM32_%s_TABLE" % Name,
for Reg in RegClass:
print '\\\n X({Reg})'.format(Reg=Reg),
sys.stdout.write(' \\\n X({Reg})'.format(Reg=Reg))
print '\n'
print "#endif // SUBZERO_SRC_ICEREGISTERSARM32_DEF",
src/IceInst.cpp
......@@ -947,7 +947,9 @@ void InstFakeDef::emit(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrEmit();
Str << "\t# ";
getDest()->emit(Func);
Str << " = def.pseudo ";
Str << " = def.pseudo";
if (getSrcSize() > 0)
Str << " ";
emitSources(Func);
Str << "\n";
}
......
src/IceRegistersARM32.def
......@@ -4,7 +4,6 @@
#ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF
#define SUBZERO_SRC_ICEREGISTERSARM32_DEF
//define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
#define REGARM32_GPR_TABLE \
X(Reg_r0, 0, "r0", 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r0, r0r1)) \
......@@ -22,8 +21,7 @@
X(Reg_ip, 12, "ip", 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, ip)) \
X(Reg_sp, 13, "sp", 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, sp)) \
X(Reg_lr, 14, "lr", 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, lr)) \
X(Reg_pc, 15, "pc", 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, pc))
X(Reg_pc, 15, "pc", 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, pc))
//define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
#define REGARM32_I64PAIR_TABLE \
......@@ -32,8 +30,7 @@
X(Reg_r4r5, 4, "r4, r5", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r4r5, r4, r5)) \
X(Reg_r6r7, 6, "r6, r7", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r6r7, r6, r7)) \
X(Reg_r8r9, 8, "r8, r9", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r8r9, r8, r9)) \
X(Reg_r10fp, 10, "r10, fp", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r10fp, r10, fp))
X(Reg_r10fp, 10, "r10, fp", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r10fp, r10, fp))
//define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
#define REGARM32_FP32_TABLE \
......@@ -68,8 +65,7 @@
X(Reg_s28, 28, "s28", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s28, d14, q7)) \
X(Reg_s29, 29, "s29", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s29, d14, q7)) \
X(Reg_s30, 30, "s30", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s30, d15, q7)) \
X(Reg_s31, 31, "s31", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s31, d15, q7))
X(Reg_s31, 31, "s31", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s31, d15, q7))
//define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
#define REGARM32_FP64_TABLE \
......@@ -104,8 +100,7 @@
X(Reg_d28, 28, "d28", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d28, q14)) \
X(Reg_d29, 29, "d29", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d29, q14)) \
X(Reg_d30, 30, "d30", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d30, q15)) \
X(Reg_d31, 31, "d31", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d31, q15))
X(Reg_d31, 31, "d31", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d31, q15))
//define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
#define REGARM32_VEC128_TABLE \
......@@ -124,6 +119,6 @@
X(Reg_q12, 12, "q12", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q12, d24, d25)) \
X(Reg_q13, 13, "q13", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q13, d26, d27)) \
X(Reg_q14, 14, "q14", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q14, d28, d29)) \
X(Reg_q15, 15, "q15", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q15, d30, d31))
X(Reg_q15, 15, "q15", 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST3(RegARM32, q15, d30, d31))
#endif // SUBZERO_SRC_ICEREGISTERSARM32_DEF
tests_lit/assembler/arm32/bic.ll
......@@ -60,7 +60,7 @@ define internal i32 @AllocBigAlign() {
; IASM-NEXT: .byte 0xcd
; IASM-NEXT: .byte 0xe3
; ASM-NEXT: # sp = def.pseudo
; ASM-NEXT: # sp = def.pseudo
; ASM-NEXT: add r0, sp, #0
; DIS-NEXT: 10: e28d0000
......@@ -83,7 +83,7 @@ define internal i32 @AllocBigAlign() {
; IASM-NEXT: .byte 0x9d
; IASM-NEXT: .byte 0xe4
; ASM-NEXT: # fp = def.pseudo
; ASM-NEXT: # fp = def.pseudo
; ASM-NEXT: bx lr
; DIS-NEXT: 1c: e12fff1e
......
tests_lit/assembler/arm32/clz.ll
......@@ -37,7 +37,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: str r0, [sp, #4]
; ASM-NEXT: # [sp, #4] = def.pseudo
; ASM-NEXT: # [sp, #4] = def.pseudo
; DIS-NEXT: 4: e58d0004
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
......
tests_lit/assembler/arm32/cmn.ll
......@@ -35,7 +35,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: str r0, [sp, #8]
; ASM-NEXT: # [sp, #8] = def.pseudo
; ASM-NEXT: # [sp, #8] = def.pseudo
; DIS-NEXT: 4: e58d0008
; IASM-NEXT: .byte 0x8
; IASM-NEXT: .byte 0x0
......
tests_lit/assembler/arm32/cmp.ll
......@@ -39,7 +39,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: str r0, [sp, #20]
; ASM-NEXT: # [sp, #20] = def.pseudo
; ASM-NEXT: # [sp, #20] = def.pseudo
; DIS-NEXT: 4: e58d0014
; IASM-NEXT: .byte 0x14
; IASM-NEXT: .byte 0x0
......@@ -47,7 +47,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r1, [sp, #16]
; ASM-NEXT: # [sp, #16] = def.pseudo
; ASM-NEXT: # [sp, #16] = def.pseudo
; DIS-NEXT: 8: e58d1010
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x10
......@@ -62,7 +62,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: strb r0, [sp, #12]
; ASM-NEXT: # [sp, #12] = def.pseudo
; ASM-NEXT: # [sp, #12] = def.pseudo
; DIS-NEXT: 10: e5cd000c
; IASM-NEXT: .byte 0xc
; IASM-NEXT: .byte 0x0
......@@ -77,7 +77,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: strb r0, [sp, #8]
; ASM-NEXT: # [sp, #8] = def.pseudo
; ASM-NEXT: # [sp, #8] = def.pseudo
; DIS-NEXT: 18: e5cd0008
; IASM-NEXT: .byte 0x8
; IASM-NEXT: .byte 0x0
......@@ -144,7 +144,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: str r0, [sp, #12]
; ASM-NEXT: # [sp, #12] = def.pseudo
; ASM-NEXT: # [sp, #12] = def.pseudo
; DIS-NEXT: 54: e58d000c
; IASM-NEXT: .byte 0xc
; IASM-NEXT: .byte 0x0
......@@ -152,7 +152,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r1, [sp, #8]
; ASM-NEXT: # [sp, #8] = def.pseudo
; ASM-NEXT: # [sp, #8] = def.pseudo
; DIS-NEXT: 58: e58d1008
; IASM-NEXT: .byte 0x8
; IASM-NEXT: .byte 0x10
......
tests_lit/assembler/arm32/dmb.ll
......@@ -37,7 +37,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: str r0, [sp, #8]
; ASM-NEXT: # [sp, #8] = def.pseudo
; ASM-NEXT: # [sp, #8] = def.pseudo
; DIS-NEXT: 4: e58d0008
; IASM-NEXT: .byte 0x8
; IASM-NEXT: .byte 0x0
......
tests_lit/assembler/arm32/ldr-str-more.ll
......@@ -36,7 +36,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: str r0, [sp, #28]
; ASM-NEXT: # [sp, #28] = def.pseudo
; ASM-NEXT: # [sp, #28] = def.pseudo
; DIS-NEXT: 4: e58d001c
; IASM-NEXT: .byte 0x1c
; IASM-NEXT: .byte 0x0
......@@ -44,7 +44,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r1, [sp, #24]
; ASM-NEXT: # [sp, #24] = def.pseudo
; ASM-NEXT: # [sp, #24] = def.pseudo
; DIS-NEXT: 8: e58d1018
; IASM-NEXT: .byte 0x18
; IASM-NEXT: .byte 0x10
......@@ -68,7 +68,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: strb r0, [sp, #20]
; ASM-NEXT: # [sp, #20] = def.pseudo
; ASM-NEXT: # [sp, #20] = def.pseudo
; DIS-NEXT: 14: e5cd0014
; IASM-NEXT: .byte 0x14
; IASM-NEXT: .byte 0x0
......@@ -93,7 +93,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: strb r0, [sp, #16]
; ASM-NEXT: # [sp, #16] = def.pseudo
; ASM-NEXT: # [sp, #16] = def.pseudo
; DIS-NEXT: 20: e5cd0010
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0
......@@ -110,7 +110,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r0, [sp, #12]
; ASM-NEXT: # [sp, #12] = def.pseudo
; ASM-NEXT: # [sp, #12] = def.pseudo
; DIS-NEXT: 28: e58d000c
; IASM-NEXT: .byte 0xc
; IASM-NEXT: .byte 0x0
......@@ -155,7 +155,7 @@ entry:
; IASM-NEXT: .byte 0x11
; ASM-NEXT: str r0, [sp, #8]
; ASM-NEXT: # [sp, #8] = def.pseudo
; ASM-NEXT: # [sp, #8] = def.pseudo
; DIS-NEXT: 40: e58d0008
; IASM-NEXT: .byte 0x8
; IASM-NEXT: .byte 0x0
......@@ -200,7 +200,7 @@ entry:
; IASM-NEXT: .byte 0x13
; ASM-NEXT: strb r0, [sp, #4]
; ASM-NEXT: # [sp, #4] = def.pseudo
; ASM-NEXT: # [sp, #4] = def.pseudo
; DIS-NEXT: 58: e5cd0004
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
......@@ -217,7 +217,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r0, [sp]
; ASM-NEXT: # [sp] = def.pseudo
; ASM-NEXT: # [sp] = def.pseudo
; DIS-NEXT: 60: e58d0000
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
......@@ -264,7 +264,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: str r0, [sp, #32]
; ASM-NEXT: # [sp, #32] = def.pseudo
; ASM-NEXT: # [sp, #32] = def.pseudo
; DIS-NEXT: 74: e58d0020
; IASM-NEXT: .byte 0x20
; IASM-NEXT: .byte 0x0
......@@ -272,7 +272,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r1, [sp, #28]
; ASM-NEXT: # [sp, #28] = def.pseudo
; ASM-NEXT: # [sp, #28] = def.pseudo
; DIS-NEXT: 78: e58d101c
; IASM-NEXT: .byte 0x1c
; IASM-NEXT: .byte 0x10
......@@ -289,7 +289,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: strh r0, [sp, #24]
; ASM-NEXT: # [sp, #24] = def.pseudo
; ASM-NEXT: # [sp, #24] = def.pseudo
; DIS-NEXT: 80: e1cd01b8
; IASM-NEXT: .byte 0xb8
; IASM-NEXT: .byte 0x1
......@@ -306,7 +306,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: strh r0, [sp, #20]
; ASM-NEXT: # [sp, #20] = def.pseudo
; ASM-NEXT: # [sp, #20] = def.pseudo
; DIS-NEXT: 88: e1cd01b4
; IASM-NEXT: .byte 0xb4
; IASM-NEXT: .byte 0x1
......@@ -330,7 +330,7 @@ entry:
; IASM-NEXT: .byte 0xe6
; ASM-NEXT: str r0, [sp, #16]
; ASM-NEXT: # [sp, #16] = def.pseudo
; ASM-NEXT: # [sp, #16] = def.pseudo
; DIS-NEXT: 94: e58d0010
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0
......@@ -354,7 +354,7 @@ entry:
; IASM-NEXT: .byte 0xe6
; ASM-NEXT: str r0, [sp, #12]
; ASM-NEXT: # [sp, #12] = def.pseudo
; ASM-NEXT: # [sp, #12] = def.pseudo
; DIS-NEXT: a0: e58d000c
; IASM-NEXT: .byte 0xc
; IASM-NEXT: .byte 0x0
......@@ -385,7 +385,7 @@ entry:
; IASM-NEXT: .byte 0xe0
; ASM-NEXT: str r0, [sp, #8]
; ASM-NEXT: # [sp, #8] = def.pseudo
; ASM-NEXT: # [sp, #8] = def.pseudo
; DIS-NEXT: b0: e58d0008
; IASM-NEXT: .byte 0x8
; IASM-NEXT: .byte 0x0
......@@ -402,7 +402,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: strh r0, [sp, #4]
; ASM-NEXT: # [sp, #4] = def.pseudo
; ASM-NEXT: # [sp, #4] = def.pseudo
; DIS-NEXT: b8: e1cd00b4
; IASM-NEXT: .byte 0xb4
; IASM-NEXT: .byte 0x0
......@@ -426,7 +426,7 @@ entry:
; IASM-NEXT: .byte 0xe6
; ASM-NEXT: str r0, [sp]
; ASM-NEXT: # [sp] = def.pseudo
; ASM-NEXT: # [sp] = def.pseudo
; DIS-NEXT: c4: e58d0000
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
......
tests_lit/assembler/arm32/ldrex-strex.ll
......@@ -43,7 +43,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: str r0, [sp, #24]
; ASM-NEXT: # [sp, #24] = def.pseudo
; ASM-NEXT: # [sp, #24] = def.pseudo
; DIS-NEXT: 4: e58d0018
; IASM-NEXT: .byte 0x18
; IASM-NEXT: .byte 0x0
......@@ -51,7 +51,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r1, [sp, #20]
; ASM-NEXT: # [sp, #20] = def.pseudo
; ASM-NEXT: # [sp, #20] = def.pseudo
; DIS-NEXT: 8: e58d1014
; IASM-NEXT: .byte 0x14
; IASM-NEXT: .byte 0x10
......@@ -70,7 +70,7 @@ entry:
; ASM-NEXT: strb r0, [sp, #16]
; DIS-NEXT: 10: e5cd0010
; ASM-NEXT: # [sp, #16] = def.pseudo
; ASM-NEXT: # [sp, #16] = def.pseudo
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0xcd
......@@ -87,7 +87,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: strb r0, [sp, #4]
; ASM-NEXT: # [sp, #4] = def.pseudo
; ASM-NEXT: # [sp, #4] = def.pseudo
; DIS-NEXT: 18: e5cd0004
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
......@@ -102,7 +102,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r0, [sp]
; ASM-NEXT: # [sp] = def.pseudo
; ASM-NEXT: # [sp] = def.pseudo
; DIS-NEXT: 20: e58d0000
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
......@@ -149,7 +149,7 @@ entry:
; IASM-NEXT: .byte 0xe1
; ASM-NEXT: add r1, r2, r1
; ASM-NEXT: # r3 = def.pseudo
; ASM-NEXT: # r3 = def.pseudo
; DIS-NEXT: 38: e0821001
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10
......@@ -185,7 +185,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: str r0, [sp, #24]
; ASM-NEXT: # [sp, #24] = def.pseudo
; ASM-NEXT: # [sp, #24] = def.pseudo
; DIS-NEXT: 74: e58d0018
; IASM-NEXT: .byte 0x18
; IASM-NEXT: .byte 0x0
......@@ -193,7 +193,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r1, [sp, #20]
; ASM-NEXT: # [sp, #20] = def.pseudo
; ASM-NEXT: # [sp, #20] = def.pseudo
; DIS-NEXT: 78: e58d1014
; IASM-NEXT: .byte 0x14
; IASM-NEXT: .byte 0x10
......@@ -211,7 +211,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: strh r0, [sp, #16]
; ASM-NEXT: # [sp, #16] = def.pseudo
; ASM-NEXT: # [sp, #16] = def.pseudo
; DIS-NEXT: 80: e1cd01b0
; IASM-NEXT: .byte 0xb0
; IASM-NEXT: .byte 0x1
......@@ -229,7 +229,7 @@ entry:
; IASM-NEXT: .byte 0xe1
; ASM-NEXT: strh r0, [sp, #4]
; ASM-NEXT: # [sp, #4] = def.pseudo
; ASM-NEXT: # [sp, #4] = def.pseudo
; DIS-NEXT: 88: e1cd00b4
; IASM-NEXT: .byte 0xb4
; IASM-NEXT: .byte 0x0
......@@ -244,7 +244,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r0, [sp]
; ASM-NEXT: # [sp] = def.pseudo
; ASM-NEXT: # [sp] = def.pseudo
; DIS-NEXT: 90: e58d0000
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
......@@ -291,7 +291,7 @@ entry:
; IASM-NEXT: .byte 0xe1
; ASM-NEXT: add r1, r2, r1
; ASM-NEXT: # r3 = def.pseudo
; ASM-NEXT: # r3 = def.pseudo
; DIS-NEXT: a8: e0821001
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10
......@@ -327,7 +327,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: str r0, [sp, #16]
; ASM-NEXT: # [sp, #16] = def.pseudo
; ASM-NEXT: # [sp, #16] = def.pseudo
; DIS-NEXT: e4: e58d0010
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0
......@@ -335,7 +335,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r1, [sp, #12]
; ASM-NEXT: # [sp, #12] = def.pseudo
; ASM-NEXT: # [sp, #12] = def.pseudo
; DIS-NEXT: e8: e58d100c
; IASM-NEXT: .byte 0xc
; IASM-NEXT: .byte 0x10
......@@ -354,7 +354,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r0, [sp, #4]
; ASM-NEXT: # [sp, #4] = def.pseudo
; ASM-NEXT: # [sp, #4] = def.pseudo
; DIS-NEXT: f0: e58d0004
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
......@@ -369,7 +369,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r0, [sp]
; ASM-NEXT: # [sp] = def.pseudo
; ASM-NEXT: # [sp] = def.pseudo
; DIS-NEXT: f8: e58d0000
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
......@@ -409,7 +409,7 @@ entry:
; IASM-NEXT: .byte 0xe1
; ASM-NEXT: add r1, r2, r1
; ASM-NEXT: # r3 = def.pseudo
; ASM-NEXT: # r3 = def.pseudo
; DIS-NEXT: 10c: e0821001
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0x10
......@@ -451,7 +451,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: str r0, [sp, #28]
; ASM-NEXT: # [sp, #28] = def.pseudo
; ASM-NEXT: # [sp, #28] = def.pseudo
; DIS-NEXT: 138: e58d001c
; IASM-NEXT: .byte 0x1c
; IASM-NEXT: .byte 0x0
......@@ -466,7 +466,7 @@ entry:
; IASM-NEXT: .byte 0xe1
; ASM-NEXT: str r0, [sp, #24]
; ASM-NEXT: # [sp, #24] = def.pseudo
; ASM-NEXT: # [sp, #24] = def.pseudo
; DIS-NEXT: 140: e58d0018
; IASM-NEXT: .byte 0x18
; IASM-NEXT: .byte 0x0
......@@ -481,8 +481,8 @@ entry:
; IASM-NEXT: .byte 0xe1
; ASM-NEXT: str r0, [sp, #20]
; ASM-NEXT: # [sp, #20] = def.pseudo
; ASM-NEXT: # [sp] = def.pseudo
; ASM-NEXT: # [sp, #20] = def.pseudo
; ASM-NEXT: # [sp] = def.pseudo
; DIS-NEXT: 148: e58d0014
; IASM-NEXT: .byte 0x14
; IASM-NEXT: .byte 0x0
......@@ -501,7 +501,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r0, [sp, #8]
; ASM-NEXT: # [sp, #8] = def.pseudo
; ASM-NEXT: # [sp, #8] = def.pseudo
; DIS-NEXT: 150: e58d0008
; IASM-NEXT: .byte 0x8
; IASM-NEXT: .byte 0x0
......@@ -516,7 +516,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r0, [sp, #4]
; ASM-NEXT: # [sp, #4] = def.pseudo
; ASM-NEXT: # [sp, #4] = def.pseudo
; DIS-NEXT: 158: e58d0004
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
......@@ -531,7 +531,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r0, [sp]
; ASM-NEXT: # [sp] = def.pseudo
; ASM-NEXT: # [sp] = def.pseudo
; DIS-NEXT: 160: e58d0000
; IASM-NEXT: .byte 0x0
; IASM-NEXT: .byte 0x0
......@@ -603,7 +603,7 @@ entry:
; IASM-NEXT: .byte 0xe0
; ASM-NEXT: adc r3, r5, r3
; ASM-NEXT: # r1 = def.pseudo
; ASM-NEXT: # r1 = def.pseudo
; DIS-NEXT: 184: e0a53003
; IASM-NEXT: .byte 0x3
; IASM-NEXT: .byte 0x30
......
tests_lit/assembler/arm32/load-store.ll
......@@ -84,4 +84,3 @@ define internal i32 @add1ToR0(i32 %p) {
; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0x2f
; IASM-NEXT: .byte 0xe1
tests_lit/assembler/arm32/mls.ll
......@@ -35,7 +35,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: str r0, [sp, #8]
; ASM-NEXT: # [sp, #8] = def.pseudo
; ASM-NEXT: # [sp, #8] = def.pseudo
; DIS-NEXT: 4: e58d0008
; IASM-NEXT: .byte 0x8
; IASM-NEXT: .byte 0x0
......@@ -43,7 +43,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r1, [sp, #4]
; ASM-NEXT: # [sp, #4] = def.pseudo
; ASM-NEXT: # [sp, #4] = def.pseudo
; DIS-NEXT: 8: e58d1004
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x10
......
tests_lit/assembler/arm32/mov-imm.ll
......@@ -37,7 +37,7 @@ define internal i32 @Imm1() {
define internal i32 @rotateFImmAA() {
; immediate = 0x000002a8 = b 0000 0000 0000 0000 0000 0010 1010 1000
ret i32 680
ret i32 680
}
; ASM-LABEL: rotateFImmAA:
......@@ -71,7 +71,7 @@ define internal i32 @rotateEImmAA() {
define internal i32 @rotateDImmAA() {
; immediate = 0x00002a80 = b 0000 0000 0000 0000 0010 1010 1000 0000
ret i32 10880
ret i32 10880
}
; ASM-LABEL: rotateDImmAA:
......@@ -88,7 +88,7 @@ define internal i32 @rotateDImmAA() {
define internal i32 @rotateCImmAA() {
; immediate = 0x0000aa00 = b 0000 0000 0000 0000 1010 1010 0000 0000
ret i32 43520
ret i32 43520
}
; ASM-LABEL: rotateCImmAA:
......@@ -105,7 +105,7 @@ define internal i32 @rotateCImmAA() {
define internal i32 @rotateBImmAA() {
; immediate = 0x0002a800 = b 0000 0000 0000 0010 1010 1000 0000 0000
ret i32 174080
ret i32 174080
}
; ASM-LABEL: rotateBImmAA:
......@@ -122,7 +122,7 @@ define internal i32 @rotateBImmAA() {
define internal i32 @rotateAImmAA() {
; immediate = 0x000aa000 = b 0000 0000 0000 1010 1010 0000 0000 0000
ret i32 696320
ret i32 696320
}
; ASM-LABEL: rotateAImmAA:
......
tests_lit/assembler/arm32/mvn.ll
......@@ -35,7 +35,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: str r0, [sp, #20]
; ASM-NEXT: # [sp, #20] = def.pseudo
; ASM-NEXT: # [sp, #20] = def.pseudo
; DIS-NEXT: 4: e58d0014
; IASM-NEXT: .byte 0x14
; IASM-NEXT: .byte 0x0
......@@ -43,7 +43,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r1, [sp, #16]
; ASM-NEXT: # [sp, #16] = def.pseudo
; ASM-NEXT: # [sp, #16] = def.pseudo
; DIS-NEXT: 8: e58d1010
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x10
......@@ -67,7 +67,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: strb r0, [sp, #12]
; ASM-NEXT: # [sp, #12] = def.pseudo
; ASM-NEXT: # [sp, #12] = def.pseudo
; DIS-NEXT: 14: e5cd000c
; IASM-NEXT: .byte 0xc
; IASM-NEXT: .byte 0x0
......@@ -91,7 +91,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: strb r0, [sp, #8]
; ASM-NEXT: # [sp, #8] = def.pseudo
; ASM-NEXT: # [sp, #8] = def.pseudo
; DIS-NEXT: 20: e5cd0008
; IASM-NEXT: .byte 0x8
; IASM-NEXT: .byte 0x0
......@@ -108,7 +108,7 @@ entry:
; IASM-NEXT: .byte 0xe5
; ASM-NEXT: str r0, [sp, #4]
; ASM-NEXT: # [sp, #4] = def.pseudo
; ASM-NEXT: # [sp, #4] = def.pseudo
; DIS-NEXT: 28: e58d0004
; IASM-NEXT: .byte 0x4
; IASM-NEXT: .byte 0x0
......
tests_lit/assembler/arm32/push-pop.ll
......@@ -36,7 +36,7 @@ define internal void @SinglePushPop() {
; IASM-NOT: push
call void @DoSomething();
ret void
ret void
; ASM: pop {lr}
; DIS: {{.+}} e49de004
......
tests_lit/assembler/arm32/rsb.ll
......@@ -2,7 +2,7 @@
; uses rsb for type i64.
; Also shows an example of a register-shifted register (data) operation.
; REQUIRES: allow_dump
; Compile using standalone assembler.
......@@ -38,7 +38,7 @@ entry:
; IASM-NEXT: .byte 0xe2
; ASM-NEXT: str r0, [sp, #20]
; ASM-NEXT: # [sp, #20] = def.pseudo
; ASM-NEXT: # [sp, #20] = def.pseudo
; DIS-NEXT: 4: e58d0014
; IASM-NEXT: .byte 0x14
; IASM-NEXT: .byte 0x0
......@@ -53,7 +53,7 @@ entry:
; IASM-NEXT: .byte 0xe1
; ASM-NEXT: str r0, [sp, #16]
; ASM-NEXT: # [sp, #16] = def.pseudo
; ASM-NEXT: # [sp, #16] = def.pseudo
; DIS-NEXT: c: e58d0010
; IASM-NEXT: .byte 0x10
; IASM-NEXT: .byte 0x0
......@@ -68,7 +68,7 @@ entry:
; IASM-NEXT: .byte 0xe1
; ASM-NEXT: str r0, [sp, #12]
; ASM-NEXT: # [sp, #12] = def.pseudo
; ASM-NEXT: # [sp, #12] = def.pseudo
; DIS-NEXT: 14: e58d000c
; IASM-NEXT: .byte 0xc
; IASM-NEXT: .byte 0x0
......@@ -83,7 +83,7 @@ entry:
; IASM-NEXT: .byte 0xe1
; ASM-NEXT: str r0, [sp, #8]
; ASM-NEXT: # [sp, #8] = def.pseudo
; ASM-NEXT: # [sp, #8] = def.pseudo
; DIS-NEXT: 1c: e58d0008
; IASM-NEXT: .byte 0x8
; IASM-NEXT: .byte 0x0
......
tests_lit/assembler/arm32/sandboxing.ll
......@@ -60,7 +60,7 @@ next3:
; CHECK-NEXT: nop
; CHECK-NEXT: bic [[REG]], [[REG]], {{.+}} ; 0xc000000f
; CHECK-NEXT: blx r0
; CHECk-NEXT: {{[0-9a-f]*}}0:
; CHECK-NEXT: {{[0-9a-f]*}}0:
; Same as above, but force bundle padding by adding two (branch) instruction
; before the tested call.
......@@ -88,7 +88,7 @@ next2:
; CHECK-NEXT: nop
; CHECK-NEXT: bic [[REG]], [[REG]], {{.+}} ; 0xc000000f
; CHECK-NEXT: blx r0
; CHECk-NEXT: {{[0-9a-f]*}}0:
; CHECK-NEXT: {{[0-9a-f]*}}0:
; Same as above, but force bundle padding by adding single (branch) instruction
; before the tested call.
......@@ -114,7 +114,7 @@ next:
; CHECK-NEXT: nop
; CHECK-NEXT: bic [[REG]], [[REG]], {{.+}} ; 0xc000000f
; CHECK-NEXT: blx r0
; CHECk-NEXT: {{[0-9a-f]*}}0:
; CHECK-NEXT: {{[0-9a-f]*}}0:
; An indirect call sequence uses the right mask and register-call sequence.
define internal void @test_indirect_call(i32 %target) {
......@@ -136,7 +136,7 @@ next:
; CHECK-NEXT: ldr
; CHECK-NEXT: bic [[REG:r[0-3]]], [[REG]], {{.*}} 0xc000000f
; CHECK-NEXT: blx [[REG]]
; CHECk-NEXT: {{[0-9]+}}0:
; CHECK-NEXT: {{[0-9]+}}0:
; An indirect call sequence uses the right mask and register-call sequence.
; Forces bundling before the tested call.
......@@ -156,7 +156,7 @@ entry:
; CHECK-NEXT: nop
; CHECK-NEXT: bic [[REG:r[0-3]]], [[REG]], {{.*}} 0xc000000f
; CHECK-NEXT: blx [[REG]]
; CHECk-NEXT: {{[0-9]+}}0:
; CHECK-NEXT: {{[0-9]+}}0:
; An indirect call sequence uses the right mask and register-call sequence.
; Forces bundling by adding three (branch) instructions befor the tested call.
......@@ -187,7 +187,7 @@ next3:
; CHECK-NEXT: nop
; CHECK-NEXT: bic [[REG:r[0-3]]], [[REG]], {{.*}} 0xc000000f
; CHECK-NEXT: blx [[REG]]
; CHECk-NEXT: {{[0-9]+}}0:
; CHECK-NEXT: {{[0-9]+}}0:
; An indirect call sequence uses the right mask and register-call sequence.
; Forces bundling by adding two (branch) instructions befor the tested call.
......@@ -215,7 +215,7 @@ next2:
; CHECK-NEXT: nop
; CHECK-NEXT: bic [[REG:r[0-3]]], [[REG]], {{.*}} 0xc000000f
; CHECK-NEXT: blx [[REG]]
; CHECk-NEXT: {{[0-9]+}}0:
; CHECK-NEXT: {{[0-9]+}}0:
; A return sequences uses the right pop / mask / jmp sequence.
define internal void @test_ret() {
......@@ -266,7 +266,7 @@ entry:
; Search for call at end of bundle.
; CHECK: {{[0-9a-f]*}}c: {{.+}} blx
; CHECK-NEXT: mov [[REG:r[0-9]]], #0
; CHECK-NEXT: mov
; CHECK-NEXT: mov
; CHECK-NEXT: bic [[REG]], [[REG]], {{.+}} ; 0xc0000000
; CHECK-NEXT: strh r{{.+}}[[REG]]
......@@ -286,7 +286,7 @@ next:
; CHECK: {{[0-9a-f]*}}c: {{.+}} blx
; CHECK-NEXT: b
; CHECK-NEXT: mov [[REG:r[0-9]]], #0
; CHECK-NEXT: mov
; CHECK-NEXT: mov
; CHECK-NEXT: nop
; CHECK-NEXT: bic [[REG]], [[REG]], {{.+}} ; 0xc0000000
; CHECK-NEXT: strh r{{.+}}[[REG]]
......
tests_lit/assembler/arm32/uxtb.ll
......@@ -87,4 +87,3 @@ entry:
; IASM-NEXT: .byte 0xe1
}
tests_lit/assembler/arm32/vldr.ll
......@@ -49,7 +49,7 @@ entry:
; ASM: .LtestDouble$entry:
; %vaddr = bitcast [8 x i8]* @doubleVal to double*
%vaddr = inttoptr i32 0 to double*
%vaddr = inttoptr i32 0 to double*
%v = load double, double* %vaddr, align 1
; ASM: vldr d20, [r5]
......
tests_lit/llvm2ice_tests/64bit.pnacl.ll
......@@ -1960,4 +1960,3 @@ branch2:
; ARM32-LABEL: phi64Undef
; ARM32: mov {{.*}} #0
; ARM32: mov {{.*}} #0
tests_lit/llvm2ice_tests/globalrelocs.ll
......@@ -263,4 +263,3 @@ define internal void @func() {
}
; DUMP: define internal void @func() {
tests_lit/llvm2ice_tests/rng.ll
......@@ -9,7 +9,7 @@
; RUN: %p2i --target x8632 -i %s --filetype=obj --disassemble --args -O2 \
; RUN: -sz-seed=1 -randomize-pool-immediates=randomize \
; RUN: -randomize-pool-threshold=0x1 \
; RUN: -reorder-global-variables \
; RUN: -reorder-global-variables \
; RUN: -reorder-basic-blocks \
; RUN: -reorder-functions \
; RUN: -randomize-regalloc \
......@@ -23,7 +23,7 @@
; RUN: --args -O2 -sz-seed=1 \
; RUN: -randomize-pool-immediates=randomize \
; RUN: -randomize-pool-threshold=0x1 \
; RUN: -reorder-global-variables \
; RUN: -reorder-global-variables \
; RUN: -reorder-basic-blocks \
; RUN: -reorder-functions \
; RUN: -randomize-regalloc \
......@@ -35,7 +35,7 @@
; RUN: %p2i --target x8632 -i %s --filetype=asm --args -O2 -sz-seed=1\
; RUN: -randomize-pool-immediates=randomize \
; RUN: -randomize-pool-threshold=0x1 \
; RUN: -reorder-global-variables \
; RUN: -reorder-global-variables \
; RUN: -reorder-basic-blocks \
; RUN: -reorder-functions \
; RUN: -randomize-regalloc \
......@@ -47,7 +47,7 @@
; RUN: %p2i --target x8632 -i %s --filetype=obj --disassemble --args -O2 \
; RUN: -sz-seed=1 -randomize-pool-immediates=randomize \
; RUN: -randomize-pool-threshold=0x1 \
; RUN: -reorder-global-variables \
; RUN: -reorder-global-variables \
; RUN: -reorder-basic-blocks \
; RUN: -reorder-functions \
; RUN: -randomize-regalloc \
......@@ -59,7 +59,7 @@
; RUN: %p2i --target x8632 -i %s --filetype=obj --disassemble --args -O2 \
; RUN: -sz-seed=1 -randomize-pool-immediates=randomize \
; RUN: -randomize-pool-threshold=0x1 \
; RUN: -reorder-global-variables \
; RUN: -reorder-global-variables \
; RUN: -reorder-basic-blocks \
; RUN: -reorder-functions \
; RUN: -randomize-regalloc \
......@@ -70,7 +70,7 @@
; Command for checking nop insertion (Need to turn off randomize-regalloc)
; RUN: %p2i --target x8632 -i %s --filetype=asm --args \
; RUN: -sz-seed=1 -randomize-pool-immediates=randomize \
; RUN: -reorder-global-variables \
; RUN: -reorder-global-variables \
; RUN: -reorder-basic-blocks \
; RUN: -reorder-functions \
; RUN: -randomize-regalloc=0 \
......@@ -83,7 +83,7 @@
; RUN: --args -O2 -sz-seed=1 \
; RUN: -randomize-pool-immediates=randomize \
; RUN: -randomize-pool-threshold=0x1 \
; RUN: -reorder-global-variables \
; RUN: -reorder-global-variables \
; RUN: -reorder-basic-blocks \
; RUN: -reorder-functions \
; RUN: -randomize-regalloc \
......
tests_lit/llvm2ice_tests/unknown-arm-reg.ll
......@@ -10,4 +10,3 @@ define void @foo() {
}
; CHECK: LLVM ERROR: Unrecognized use/exclude registers: xx9x yy28 sq5
tests_lit/parse_errs/bad-bb-size.test
......@@ -8,4 +8,3 @@
; RUN: | FileCheck %s
; CHECK: Function defines 3105555534 basic blocks, which is too big for a function containing 36 bytes
tests_lit/parse_errs/bad-global-alignment.test
......@@ -9,4 +9,3 @@
; RUN: | FileCheck %s
; CHECK: Global variable alignment greater than 2**29. Found: 2**30
tests_lit/parse_errs/bad-var-fwdref.test
......@@ -8,4 +8,3 @@
; RUN: | FileCheck %s
; CHECK: Forward reference @3105555534 too big. Have 1 globals and function contains 16 bytes
tests_lit/parse_errs/call-fcn-bad-param-type.test
......@@ -47,7 +47,3 @@
; DIS-NEXT: ret void;
; DIS-NEXT: }
; DIS-NEXT: }
tests_lit/parse_errs/call-fcn-bad-return-type.ll
......@@ -17,4 +17,3 @@ entry:
; CHECK: Return type of function is invalid: i1
ret void
}
tests_lit/parse_errs/dup-module-vst.test
......@@ -19,4 +19,3 @@
; ASM: @f0 : "f";
; ASM: }
; ASM: }
tests_lit/parse_errs/fcn-value-index-isnt-defined.test
......@@ -41,4 +41,3 @@
; ASM: Error({{.*}}): Can't find type for %v1
; ASM: }
; ASM: }
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