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Commit fbdc7e4c by Jim Stichnoth
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Subzero: Fix trailing whitespace errors.

To view the non-whitespace changes in this CL: git cl patch -b testbranch 1678133003 git diff -w --ignore-blank-lines -b master Such changes are only in gen_arm32_reg_tables.py and IceInst.cpp. There are lots of tab characters in .ll files that shouldn't be there, but fixing them would require some thought about how to do consistent formatting, so that's left for later. BUG= none R=eholk@chromium.org, kschimpf@google.com Review URL: https://codereview.chromium.org/1678133003 .
parent d91cbbfa
Showing with 12 additions and 31 deletions
Makefile
...@@ -28,4 +28,3 @@ else ...@@ -28,4 +28,3 @@ else
-DALLOW_LLVM_IR_AS_INPUT=1 -DALLOW_MINIMAL_BUILD=0 \ -DALLOW_LLVM_IR_AS_INPUT=1 -DALLOW_MINIMAL_BUILD=0 \
-DPNACL_BROWSER_TRANSLATOR=0 -DPNACL_BROWSER_TRANSLATOR=0
endif endif
pydir/gen_arm32_reg_tables.py
...@@ -221,9 +221,9 @@ print ("// This file was auto generated by the {script} script.\n" ...@@ -221,9 +221,9 @@ print ("// This file was auto generated by the {script} script.\n"
"#define SUBZERO_SRC_ICEREGISTERSARM32_DEF\n".format(script=os.path.basename(sys.argv[0]))) "#define SUBZERO_SRC_ICEREGISTERSARM32_DEF\n".format(script=os.path.basename(sys.argv[0])))
for Name, RegClass in RegClasses: for Name, RegClass in RegClasses:
print '\n//{xmacro}'.format(xmacro=Reg.DefiningXMacro()) print '//{xmacro}'.format(xmacro=Reg.DefiningXMacro())
print "#define REGARM32_%s_TABLE" % Name, print "#define REGARM32_%s_TABLE" % Name,
for Reg in RegClass: for Reg in RegClass:
print '\\\n X({Reg})'.format(Reg=Reg), sys.stdout.write(' \\\n X({Reg})'.format(Reg=Reg))
print '\n' print '\n'
print "#endif // SUBZERO_SRC_ICEREGISTERSARM32_DEF", print "#endif // SUBZERO_SRC_ICEREGISTERSARM32_DEF",
src/IceInst.cpp
...@@ -947,7 +947,9 @@ void InstFakeDef::emit(const Cfg *Func) const { ...@@ -947,7 +947,9 @@ void InstFakeDef::emit(const Cfg *Func) const {
Ostream &Str = Func->getContext()->getStrEmit(); Ostream &Str = Func->getContext()->getStrEmit();
Str << "\t# "; Str << "\t# ";
getDest()->emit(Func); getDest()->emit(Func);
Str << " = def.pseudo "; Str << " = def.pseudo";
if (getSrcSize() > 0)
Str << " ";
emitSources(Func); emitSources(Func);
Str << "\n"; Str << "\n";
} }
......
src/IceRegistersARM32.def
...@@ -4,7 +4,6 @@ ...@@ -4,7 +4,6 @@
#ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF #ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF
#define SUBZERO_SRC_ICEREGISTERSARM32_DEF #define SUBZERO_SRC_ICEREGISTERSARM32_DEF
//define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases) //define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
#define REGARM32_GPR_TABLE \ #define REGARM32_GPR_TABLE \
X(Reg_r0, 0, "r0", 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r0, r0r1)) \ X(Reg_r0, 0, "r0", 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, REGLIST2(RegARM32, r0, r0r1)) \
...@@ -24,7 +23,6 @@ ...@@ -24,7 +23,6 @@
X(Reg_lr, 14, "lr", 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, lr)) \ X(Reg_lr, 14, "lr", 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, lr)) \
X(Reg_pc, 15, "pc", 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, pc)) X(Reg_pc, 15, "pc", 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, REGLIST1(RegARM32, pc))
//define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases) //define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
#define REGARM32_I64PAIR_TABLE \ #define REGARM32_I64PAIR_TABLE \
X(Reg_r0r1, 0, "r0, r1", 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r0r1, r0, r1)) \ X(Reg_r0r1, 0, "r0, r1", 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, REGLIST3(RegARM32, r0r1, r0, r1)) \
...@@ -34,7 +32,6 @@ ...@@ -34,7 +32,6 @@
X(Reg_r8r9, 8, "r8, r9", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r8r9, r8, r9)) \ X(Reg_r8r9, 8, "r8, r9", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r8r9, r8, r9)) \
X(Reg_r10fp, 10, "r10, fp", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r10fp, r10, fp)) X(Reg_r10fp, 10, "r10, fp", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, REGLIST3(RegARM32, r10fp, r10, fp))
//define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases) //define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
#define REGARM32_FP32_TABLE \ #define REGARM32_FP32_TABLE \
X(Reg_s0, 0, "s0", 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s0, d0, q0)) \ X(Reg_s0, 0, "s0", 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s0, d0, q0)) \
...@@ -70,7 +67,6 @@ ...@@ -70,7 +67,6 @@
X(Reg_s30, 30, "s30", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s30, d15, q7)) \ X(Reg_s30, 30, "s30", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s30, d15, q7)) \
X(Reg_s31, 31, "s31", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s31, d15, q7)) X(Reg_s31, 31, "s31", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s31, d15, q7))
//define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases) //define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
#define REGARM32_FP64_TABLE \ #define REGARM32_FP64_TABLE \
X(Reg_d0, 0, "d0", 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d0, q0, s0, s1)) \ X(Reg_d0, 0, "d0", 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d0, q0, s0, s1)) \
...@@ -106,7 +102,6 @@ ...@@ -106,7 +102,6 @@
X(Reg_d30, 30, "d30", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d30, q15)) \ X(Reg_d30, 30, "d30", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d30, q15)) \
X(Reg_d31, 31, "d31", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d31, q15)) X(Reg_d31, 31, "d31", 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d31, q15))
//define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases) //define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
#define REGARM32_VEC128_TABLE \ #define REGARM32_VEC128_TABLE \
X(Reg_q0, 0, "q0", 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q0, d0, d1, s0, s1, s2, s3)) \ X(Reg_q0, 0, "q0", 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, REGLIST7(RegARM32, q0, d0, d1, s0, s1, s2, s3)) \
......
tests_lit/assembler/arm32/load-store.ll
...@@ -84,4 +84,3 @@ define internal i32 @add1ToR0(i32 %p) { ...@@ -84,4 +84,3 @@ define internal i32 @add1ToR0(i32 %p) {
; IASM-NEXT: .byte 0xff ; IASM-NEXT: .byte 0xff
; IASM-NEXT: .byte 0x2f ; IASM-NEXT: .byte 0x2f
; IASM-NEXT: .byte 0xe1 ; IASM-NEXT: .byte 0xe1
tests_lit/assembler/arm32/sandboxing.ll
...@@ -60,7 +60,7 @@ next3: ...@@ -60,7 +60,7 @@ next3:
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: bic [[REG]], [[REG]], {{.+}} ; 0xc000000f ; CHECK-NEXT: bic [[REG]], [[REG]], {{.+}} ; 0xc000000f
; CHECK-NEXT: blx r0 ; CHECK-NEXT: blx r0
; CHECk-NEXT: {{[0-9a-f]*}}0: ; CHECK-NEXT: {{[0-9a-f]*}}0:
; Same as above, but force bundle padding by adding two (branch) instruction ; Same as above, but force bundle padding by adding two (branch) instruction
; before the tested call. ; before the tested call.
...@@ -88,7 +88,7 @@ next2: ...@@ -88,7 +88,7 @@ next2:
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: bic [[REG]], [[REG]], {{.+}} ; 0xc000000f ; CHECK-NEXT: bic [[REG]], [[REG]], {{.+}} ; 0xc000000f
; CHECK-NEXT: blx r0 ; CHECK-NEXT: blx r0
; CHECk-NEXT: {{[0-9a-f]*}}0: ; CHECK-NEXT: {{[0-9a-f]*}}0:
; Same as above, but force bundle padding by adding single (branch) instruction ; Same as above, but force bundle padding by adding single (branch) instruction
; before the tested call. ; before the tested call.
...@@ -114,7 +114,7 @@ next: ...@@ -114,7 +114,7 @@ next:
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: bic [[REG]], [[REG]], {{.+}} ; 0xc000000f ; CHECK-NEXT: bic [[REG]], [[REG]], {{.+}} ; 0xc000000f
; CHECK-NEXT: blx r0 ; CHECK-NEXT: blx r0
; CHECk-NEXT: {{[0-9a-f]*}}0: ; CHECK-NEXT: {{[0-9a-f]*}}0:
; An indirect call sequence uses the right mask and register-call sequence. ; An indirect call sequence uses the right mask and register-call sequence.
define internal void @test_indirect_call(i32 %target) { define internal void @test_indirect_call(i32 %target) {
...@@ -136,7 +136,7 @@ next: ...@@ -136,7 +136,7 @@ next:
; CHECK-NEXT: ldr ; CHECK-NEXT: ldr
; CHECK-NEXT: bic [[REG:r[0-3]]], [[REG]], {{.*}} 0xc000000f ; CHECK-NEXT: bic [[REG:r[0-3]]], [[REG]], {{.*}} 0xc000000f
; CHECK-NEXT: blx [[REG]] ; CHECK-NEXT: blx [[REG]]
; CHECk-NEXT: {{[0-9]+}}0: ; CHECK-NEXT: {{[0-9]+}}0:
; An indirect call sequence uses the right mask and register-call sequence. ; An indirect call sequence uses the right mask and register-call sequence.
; Forces bundling before the tested call. ; Forces bundling before the tested call.
...@@ -156,7 +156,7 @@ entry: ...@@ -156,7 +156,7 @@ entry:
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: bic [[REG:r[0-3]]], [[REG]], {{.*}} 0xc000000f ; CHECK-NEXT: bic [[REG:r[0-3]]], [[REG]], {{.*}} 0xc000000f
; CHECK-NEXT: blx [[REG]] ; CHECK-NEXT: blx [[REG]]
; CHECk-NEXT: {{[0-9]+}}0: ; CHECK-NEXT: {{[0-9]+}}0:
; An indirect call sequence uses the right mask and register-call sequence. ; An indirect call sequence uses the right mask and register-call sequence.
; Forces bundling by adding three (branch) instructions befor the tested call. ; Forces bundling by adding three (branch) instructions befor the tested call.
...@@ -187,7 +187,7 @@ next3: ...@@ -187,7 +187,7 @@ next3:
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: bic [[REG:r[0-3]]], [[REG]], {{.*}} 0xc000000f ; CHECK-NEXT: bic [[REG:r[0-3]]], [[REG]], {{.*}} 0xc000000f
; CHECK-NEXT: blx [[REG]] ; CHECK-NEXT: blx [[REG]]
; CHECk-NEXT: {{[0-9]+}}0: ; CHECK-NEXT: {{[0-9]+}}0:
; An indirect call sequence uses the right mask and register-call sequence. ; An indirect call sequence uses the right mask and register-call sequence.
; Forces bundling by adding two (branch) instructions befor the tested call. ; Forces bundling by adding two (branch) instructions befor the tested call.
...@@ -215,7 +215,7 @@ next2: ...@@ -215,7 +215,7 @@ next2:
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: bic [[REG:r[0-3]]], [[REG]], {{.*}} 0xc000000f ; CHECK-NEXT: bic [[REG:r[0-3]]], [[REG]], {{.*}} 0xc000000f
; CHECK-NEXT: blx [[REG]] ; CHECK-NEXT: blx [[REG]]
; CHECk-NEXT: {{[0-9]+}}0: ; CHECK-NEXT: {{[0-9]+}}0:
; A return sequences uses the right pop / mask / jmp sequence. ; A return sequences uses the right pop / mask / jmp sequence.
define internal void @test_ret() { define internal void @test_ret() {
......
tests_lit/assembler/arm32/uxtb.ll
...@@ -87,4 +87,3 @@ entry: ...@@ -87,4 +87,3 @@ entry:
; IASM-NEXT: .byte 0xe1 ; IASM-NEXT: .byte 0xe1
} }
tests_lit/llvm2ice_tests/64bit.pnacl.ll
...@@ -1960,4 +1960,3 @@ branch2: ...@@ -1960,4 +1960,3 @@ branch2:
; ARM32-LABEL: phi64Undef ; ARM32-LABEL: phi64Undef
; ARM32: mov {{.*}} #0 ; ARM32: mov {{.*}} #0
; ARM32: mov {{.*}} #0 ; ARM32: mov {{.*}} #0
tests_lit/llvm2ice_tests/globalrelocs.ll
...@@ -263,4 +263,3 @@ define internal void @func() { ...@@ -263,4 +263,3 @@ define internal void @func() {
} }
; DUMP: define internal void @func() { ; DUMP: define internal void @func() {
tests_lit/llvm2ice_tests/unknown-arm-reg.ll
...@@ -10,4 +10,3 @@ define void @foo() { ...@@ -10,4 +10,3 @@ define void @foo() {
} }
; CHECK: LLVM ERROR: Unrecognized use/exclude registers: xx9x yy28 sq5 ; CHECK: LLVM ERROR: Unrecognized use/exclude registers: xx9x yy28 sq5
tests_lit/parse_errs/bad-bb-size.test
...@@ -8,4 +8,3 @@ ...@@ -8,4 +8,3 @@
; RUN: | FileCheck %s ; RUN: | FileCheck %s
; CHECK: Function defines 3105555534 basic blocks, which is too big for a function containing 36 bytes ; CHECK: Function defines 3105555534 basic blocks, which is too big for a function containing 36 bytes
tests_lit/parse_errs/bad-global-alignment.test
...@@ -9,4 +9,3 @@ ...@@ -9,4 +9,3 @@
; RUN: | FileCheck %s ; RUN: | FileCheck %s
; CHECK: Global variable alignment greater than 2**29. Found: 2**30 ; CHECK: Global variable alignment greater than 2**29. Found: 2**30
tests_lit/parse_errs/bad-var-fwdref.test
...@@ -8,4 +8,3 @@ ...@@ -8,4 +8,3 @@
; RUN: | FileCheck %s ; RUN: | FileCheck %s
; CHECK: Forward reference @3105555534 too big. Have 1 globals and function contains 16 bytes ; CHECK: Forward reference @3105555534 too big. Have 1 globals and function contains 16 bytes
tests_lit/parse_errs/call-fcn-bad-param-type.test
...@@ -47,7 +47,3 @@ ...@@ -47,7 +47,3 @@
; DIS-NEXT: ret void; ; DIS-NEXT: ret void;
; DIS-NEXT: } ; DIS-NEXT: }
; DIS-NEXT: } ; DIS-NEXT: }
tests_lit/parse_errs/call-fcn-bad-return-type.ll
...@@ -17,4 +17,3 @@ entry: ...@@ -17,4 +17,3 @@ entry:
; CHECK: Return type of function is invalid: i1 ; CHECK: Return type of function is invalid: i1
ret void ret void
} }
tests_lit/parse_errs/dup-module-vst.test
...@@ -19,4 +19,3 @@ ...@@ -19,4 +19,3 @@
; ASM: @f0 : "f"; ; ASM: @f0 : "f";
; ASM: } ; ASM: }
; ASM: } ; ASM: }
tests_lit/parse_errs/fcn-value-index-isnt-defined.test
...@@ -41,4 +41,3 @@ ...@@ -41,4 +41,3 @@
; ASM: Error({{.*}}): Can't find type for %v1 ; ASM: Error({{.*}}): Can't find type for %v1
; ASM: } ; ASM: }
; ASM: } ; ASM: }
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