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  23. 06 Jan, 2016 1 commit
    • Subzero: Enable Non-SFI vector cross tests. · 57a8aab2
      Jim Stichnoth authored 
      The driver programs for vector tests use a loop to initialize vector-type values one element at a time.  The PNaCl ABI requires the vector element index to be a constant, and the createConstantInsertExtractElementIndexPass() transformation creates an alloca instruction.  When this alloca is inside a loop, it can (and does in the cross tests) cause a stack overflow.

The workaround here is to use a noinline helper function to do the insertelement.

We didn't run into this problem until now because native and sandbox cross tests build the driver in a different way that presumably avoids running the PNaCl ABI simplification passes.

BUG= none
R=jpp@chromium.org

Review URL: https://codereview.chromium.org/1560933002 .
  25. 04 Jan, 2016 2 commits
    • Subzero: Add Non-SFI support for x86-32. · 8ff4b281
      Jim Stichnoth authored 
      The basic model is that each translated function begins with a special "GotVar = getIP" instruction, and each ConstantRelocatable reference is changed to GotVar+ConstantRelocatable@GOTOFF (assuming GotVar is legalized into a physical register).  The getIP instruction is late-lowered into:
  call __Sz_getIP_<reg>
  add <reg>, $_GLOBAL_OFFSET_TABLE_
  mov GotVar, <reg>
Note that _GLOBAL_OFFSET_TABLE_ gets a special relocation type.

The register allocator takes GotVar uses into account, giving appropriate weight toward register allocation.

If there are no uses of GotVar, the getIP instruction gets naturally dead-code eliminated.  Special treatment is needed to prevent this elimination when the only GotVar uses are for (floating point) constant pool values from Phi instructions, since the Phi lowering with its GotVar legalization happens after the main round of register allocation.

The x86 mem operand now has a IsPIC field to indicate whether it has been PIC-legalized.  Mem operands are sometimes legalized more than once, and this IsPIC field keeps GotVar from being added more than once.

We have to limit the aggressiveness of address mode inference, to make sure a register slot is left for the GotVar.

The Subzero runtime has new asm files to implement all possible __Sz_getIP_<reg> helpers.

The szbuild.py script and the spec2k version support Non-SFI builds.  Running spec2k depends on a pending change to the spec2k run_all.sh script.

Read-only data sections need to be named .data.rel.ro instead of .rodata because of PIC rules.

Most cross tests are working, but there is some problem with vector types that seems to be not Subzero related, so most vector tests are disabled for now.

Still to do:

* Fix "--nonsfi --filetype=iasm".  The llvm-mc assembler doesn't properly apply the _GLOBAL_OFFSET_TABLE_ relocation in iasm mode.  Maybe I can find a different syntactic trick that works, or use hybrid iasm for this limited case.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4327
R=jpp@chromium.org

Review URL: https://codereview.chromium.org/1506653002 .
    • Subzero. ARM32. Materializes the register table. · 149999e5
      John Porto authored 
      This CL modifies the ARM32 backend so that the REGARM32_TABLE is only
expanded once (to initialize a constexpr array.) This change decreased
the backend size in roughly ~80k.

BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076
R=kschimpf@google.com

Review URL: https://codereview.chromium.org/1554263002 .