Add RISC-V support in cycleclock::Now (#833)

The RISC-V implementation of `cycleclock::Now` uses the user-space `rdcycle` instruction to query how many cycles have happened since the core started. The only complexity here is on 32-bit RISC-V, where `rdcycle` can only read the lower 32 bits of the 64-bit hardware counter. In this case, `rdcycleh` reads the higher 32 bits of the counter. We match the powerpc implementation to detect and correct for overflow in the high bits.

Add RISC-V support in cycleclock::Now (#833)
4abdfbb8 · Sam Elliott · Dominic Hamon · 04a9343f · 4abdfbb8
Commit 4abdfbb8 authored Jul 05, 2019 by Sam Elliott Committed by Dominic Hamon Jul 05, 2019
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cycleclock.h src/cycleclock.h +15 -0

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--- a/src/cycleclock.h
+++ b/src/cycleclock.h
@@ -164,6 +164,21 @@ inline BENCHMARK_ALWAYS_INLINE int64_t Now() {
  uint64_t tsc;
  asm("stck %0" : "=Q"(tsc) : : "cc");
  return tsc;
+#elif defined(__riscv) // RISC-V
+  // Use RDCYCLE (and RDCYCLEH on riscv32)
+#if __riscv_xlen == 32
+  uint64_t cycles_low, cycles_hi0, cycles_hi1;
+  asm("rdcycleh %0" : "=r"(cycles_hi0));
+  asm("rdcycle %0" : "=r"(cycles_lo));
+  asm("rdcycleh %0" : "=r"(cycles_hi1));
+  // This matches the PowerPC overflow detection, above
+  cycles_lo &= -static_cast<int64_t>(cycles_hi0 == cycles_hi1);
+  return (cycles_hi1 << 32) | cycles_lo;
+#else
+  uint64_t cycles;
+  asm("rdcycle %0" : "=r"(cycles));
+  return cycles;
+#endif
 #else
 // The soft failover to a generic implementation is automatic only for ARM.
 // For other platforms the developer is expected to make an attempt to create