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Commit a7c57939 by Felix Homann
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Fix cycleclock.h for gcc/ARM.

Currently there are tests for ARMV3 and ARMV6 in cycleclock.h which are not defined using gcc on ARM. Since there is also a cast to the unknown type int64 I assume that the ARM code has not been tested. Therefore this patch replaces the checks for ARMV3 and ARMV6 by checks for __ARM_ARCH. Also, the cast to int64 is fixed by casting to int64_t.
parent f835dfa8
Showing with 3 additions and 3 deletions
src/cycleclock.h
...@@ -95,8 +95,8 @@ inline ATTRIBUTE_ALWAYS_INLINE int64_t Now() { ...@@ -95,8 +95,8 @@ inline ATTRIBUTE_ALWAYS_INLINE int64_t Now() {
_asm rdtsc _asm rdtsc
#elif defined(COMPILER_MSVC) #elif defined(COMPILER_MSVC)
return __rdtsc(); return __rdtsc();
#elif defined(ARMV3) #elif defined(__ARM_ARCH)
#if defined(ARMV6) // V6 is the earliest arch that has a standard cyclecount #if (__ARM_ARCH >= 6) // V6 is the earliest arch that has a standard cyclecount
uint32_t pmccntr; uint32_t pmccntr;
uint32_t pmuseren; uint32_t pmuseren;
uint32_t pmcntenset; uint32_t pmcntenset;
...@@ -107,7 +107,7 @@ inline ATTRIBUTE_ALWAYS_INLINE int64_t Now() { ...@@ -107,7 +107,7 @@ inline ATTRIBUTE_ALWAYS_INLINE int64_t Now() {
if (pmcntenset & 0x80000000ul) { // Is it counting? if (pmcntenset & 0x80000000ul) { // Is it counting?
asm("mrc p15, 0, %0, c9, c13, 0" : "=r"(pmccntr)); asm("mrc p15, 0, %0, c9, c13, 0" : "=r"(pmccntr));
// The counter is set up to count every 64th cycle // The counter is set up to count every 64th cycle
return static_cast<int64>(pmccntr) * 64; // Should optimize to << 6 return static_cast<int64_t>(pmccntr) * 64; // Should optimize to << 6
} }
} }
#endif #endif
......
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