This is in preparation for llvm.nacl.atomic.* lowerings. atomic i64
loads and stores require their operands to be consecutive registers
starting at an even register that is not r14.

BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076
R=kschimpf@google.com

Review URL: https://codereview.chromium.org/1382063002 .