Add some missing encodings in the ARM integrated assembler.

src/IceAssemblerARM32.cpp

@@ -203,9 +203,11 @@ enum EncodedOperand {
   // Value=000000000000000000000iiiii0000000 where iiii defines the Imm5 value
   // to shift.
   EncodedAsShiftImm5,
-  // i.e. iiiiiss0mmmm where mmmm is the register to rotate, ss is the shift
+  // Value=iiiiiss0mmmm where mmmm is the register to rotate, ss is the shift
   // kind, and iiiii is the shift amount.
   EncodedAsShiftedRegister,
+  // Value=ssss0tt1mmmm where mmmm=Rm, tt is an encoded ShiftKind, and ssss=Rms.
+  EncodedAsRegShiftReg,
   // Value is 32bit integer constant.
   EncodedAsConstI32
 };
@@ -257,15 +259,29 @@ EncodedOperand encodeOperand(const Operand *Opnd, IValueT &Value) {
   }
   if (const auto *FlexReg = llvm::dyn_cast<OperandARM32FlexReg>(Opnd)) {
     Operand *Amt = FlexReg->getShiftAmt();
-    if (const auto *Imm5 = llvm::dyn_cast<OperandARM32ShAmtImm>(Amt)) {
-      IValueT Rm;
-      if (encodeOperand(FlexReg->getReg(), Rm) != EncodedAsRegister)
+    IValueT Rm;
+    if (encodeOperand(FlexReg->getReg(), Rm) != EncodedAsRegister)
+      return CantEncode;
+    if (const auto *Var = llvm::dyn_cast<Variable>(Amt)) {
+      IValueT Rs;
+      if (encodeOperand(Var, Rs) != EncodedAsRegister)
         return CantEncode;
-      Value =
-          encodeShiftRotateImm5(Rm, FlexReg->getShiftOp(), Imm5->getShAmtImm());
-      return EncodedAsShiftedRegister;
+      Value = encodeShiftRotateReg(Rm, FlexReg->getShiftOp(), Rs);
+      return EncodedAsRegShiftReg;
     }
-    // TODO(kschimpf): Handle case where Amt is a register?
+    // If reached, the amount is a shifted amount by some 5-bit immediate.
+    uint32_t Imm5;
+    if (const auto *ShAmt = llvm::dyn_cast<OperandARM32ShAmtImm>(Amt)) {
+      Imm5 = ShAmt->getShAmtImm();
+    } else if (const auto *IntConst = llvm::dyn_cast<ConstantInteger32>(Amt)) {
+      int32_t Val = IntConst->getValue();
+      if (Val < 0)
+        return CantEncode;
+      Imm5 = static_cast<uint32_t>(Val);
+    } else
+      return CantEncode;
+    Value = encodeShiftRotateImm5(Rm, FlexReg->getShiftOp(), Imm5);
+    return EncodedAsShiftedRegister;
   }
   if (const auto *ShImm = llvm::dyn_cast<OperandARM32ShAmtImm>(Opnd)) {
     const IValueT Immed5 = ShImm->getShAmtImm();
@@ -595,19 +611,19 @@ void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Opcode,
                                 IValueT Rd, IValueT Rn, const Operand *OpSrc1,
                                 bool SetFlags, EmitChecks RuleChecks,
                                 const char *InstName) {
-
   IValueT Src1Value;
   // TODO(kschimpf) Other possible decodings of data operations.
   switch (encodeOperand(OpSrc1, Src1Value)) {
   default:
-    // TODO(kschimpf): Figure out what additional cases need to be handled.
-    return setNeedsTextFixup();
+    llvm::report_fatal_error(std::string(InstName) +
+                             ": Can't encode instruction");
+    return;
   case EncodedAsRegister: {
     // XXX (register)
     //   xxx{s}<c> <Rd>, <Rn>, <Rm>{, <shiff>}
     //
-    // cccc0000100snnnnddddiiiiitt0mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
-    // mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
+    // cccc000xxxxsnnnnddddiiiiitt0mmmm where cccc=Cond, xxxx=Opcode, dddd=Rd,
+    // nnnn=Rn, mmmm=Rm, iiiii=Shift, tt=ShiftKind, and s=SetFlags.
     constexpr IValueT Imm5 = 0;
     Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Imm5);
     emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd, Src1Value,
@@ -634,12 +650,23 @@ void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Opcode,
     // XXX (Immediate)
     //   xxx{s}<c> <Rd>, <Rn>, #<RotatedImm8>
     //
-    // cccc0010100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
-    // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
+    // cccc001xxxxsnnnnddddiiiiiiiiiiii where cccc=Cond, xxxx=Opcode, dddd=Rd,
+    // nnnn=Rn, s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
     emitType01(Cond, kInstTypeDataImmediate, Opcode, SetFlags, Rn, Rd,
                Src1Value, RuleChecks, InstName);
     return;
   }
+  case EncodedAsRegShiftReg: {
+    // XXX (register-shifted reg)
+    //   xxx{s}<c> <Rd>, <Rn>, <Rm>, <type> <Rs>
+    //
+    // cccc000xxxxfnnnnddddssss0tt1mmmm where cccc=Cond, xxxx=Opcode, dddd=Rd,
+    // nnnn=Rn, ssss=Rs, f=SetFlags, tt is encoding of type, and
+    // Src1Value=ssss01tt1mmmm.
+    emitType01(Cond, kInstTypeDataRegShift, Opcode, SetFlags, Rn, Rd, Src1Value,
+               RuleChecks, InstName);
+    return;
+  }
   }
 }
 

tests_lit/assembler/arm32/mov-reg.ll

+; Show that we know how to translate mov (shifted register), which
+; are pseudo instructions for ASR, LSR, ROR, and RRX.
+
+; NOTE: We use -O2 to get rid of memory stores.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
+
+define internal i64 @testMovWithAsr(i32 %a) {
+; ASM-LABEL:testMovWithAsr:
+; DIS-LABEL:00000000 <testMovWithAsr>:
+; IASM-LABEL:testMovWithAsr:
+
+entry:
+; ASM-NEXT:.LtestMovWithAsr$entry:
+; IASM-NEXT:.LtestMovWithAsr$entry:
+
+  %a.arg_trunc = trunc i32 %a to i8
+  %conv = sext i8 %a.arg_trunc to i64
+  ret i64 %conv
+
+; ASM-NEXT:     sxtb    r0, r0
+; DIS-NEXT:   0:        e6af0070
+; IASM-NEXT:    .byte 0x70
+; IASM-NEXT:    .byte 0x0
+; IASM-NEXT:    .byte 0xaf
+; IASM-NEXT:    .byte 0xe6
+
+; ***** Example of mov pseudo instruction.
+; ASM-NEXT:     mov     r1, r0, asr #31
+; DIS-NEXT:   4:        e1a01fc0
+; IASM-NEXT:    .byte 0xc0
+; IASM-NEXT:    .byte 0x1f
+; IASM-NEXT:    .byte 0xa0
+; IASM-NEXT:    .byte 0xe1
+
+; ASM-NEXT:     bx      lr
+
+}

tests_lit/assembler/arm32/rsb.ll

 ; Show that we know how to translate rsb. Uses shl as example, because it
-; uses rsb for type i64
+; uses rsb for type i64.
+
+; Also shows an example of a register-shifted register (data) operation.
   
 ; REQUIRES: allow_dump
 
@@ -119,5 +121,20 @@ entry:
 ; IASM-NEXT:    .byte 0x62
 ; IASM-NEXT:    .byte 0xe2
 
+; ASM-NEXT:    lsr     r3, r0, r3
+; DIS-NEXT:  30:        e1a03330
+; IASM-NEXT:    .byte 0x30
+; IASM-NEXT:    .byte 0x33
+; IASM-NEXT:    .byte 0xa0
+; IASM-NEXT:    .byte 0xe1
+
+; ***** Here is an example of a register-shifted register *****
+; ASM-NEXT:    orr     r1, r3, r1, lsl r2
+; DIS-NEXT:  34:        e1831211
+; IASM-NEXT:    .byte 0x11
+; IASM-NEXT:    .byte 0x12
+; IASM-NEXT:    .byte 0x83
+; IASM-NEXT:    .byte 0xe1
+
   ret i64 %result
 }