Add translation of REV in ARM integrated assembler.

src/IceAssemblerARM32.cpp

@@ -41,6 +41,10 @@ static constexpr IValueT B4 = 1 << 4;
 static constexpr IValueT B5 = 1 << 5;
 static constexpr IValueT B6 = 1 << 6;
 static constexpr IValueT B7 = 1 << 7;
+static constexpr IValueT B8 = 1 << 8;
+static constexpr IValueT B9 = 1 << 9;
+static constexpr IValueT B10 = 1 << 10;
+static constexpr IValueT B11 = 1 << 11;
 static constexpr IValueT B12 = 1 << 12;
 static constexpr IValueT B13 = 1 << 13;
 static constexpr IValueT B14 = 1 << 14;
@@ -1591,6 +1595,23 @@ void AssemblerARM32::mul(const Operand *OpRd, const Operand *OpRn,
             MulName);
 }
 
+void AssemblerARM32::rev(const Operand *OpRd, const Operand *OpSrc,
+                         CondARM32::Cond Cond) {
+  // REV - ARM section A8.8.145, encoding A1:
+  //   rev <Rd>, <Rm>
+  //
+  // cccc011010111111dddd11110011mmmm where cccc=Cond, dddd=Rn, and mmmm=Rm.
+  constexpr const char *RevName = "rev";
+  IValueT Rd = encodeRegister(OpRd, "Rd", RevName);
+  IValueT Rm = encodeRegister(OpSrc, "Rm", RevName);
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  constexpr IValueT Opcode = B26 | B25 | B23 | B21 | B20 | B19 | B18 | B17 |
+                             B16 | B11 | B10 | B9 | B8 | B5 | B4;
+  IValueT Encoding =
+      (Cond << kConditionShift) | Opcode | (Rd << kRdShift) | (Rm << kRmShift);
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::rsb(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {

src/IceAssemblerARM32.h

@@ -258,6 +258,8 @@ public:
   // Note: Registers is a bitset, where bit n corresponds to register Rn.
   void pushList(const IValueT Registers, CondARM32::Cond Cond);
 
+  void rev(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
+
   void rsb(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
            bool SetFlags, CondARM32::Cond Cond);
 

src/IceInstARM32.cpp

@@ -1191,6 +1191,14 @@ void InstARM32UnaryopGPR<K, Nws>::emitIAS(const Cfg *Func) const {
   emitUsingTextFixup(Func);
 }
 
+template <> void InstARM32Rev::emitIAS(const Cfg *Func) const {
+  assert(getSrcSize() == 1);
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  Asm->rev(getDest(), getSrc(0), getPredicate());
+  if (Asm->needsTextFixup())
+    emitUsingTextFixup(Func);
+}
+
 template <> void InstARM32Movw::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;

tests_lit/assembler/arm32/rev.ll

+; Show that we know how to translate rev (used in bswap).
+
+; NOTE: We use -O2 to get rid of memory stores.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 | FileCheck %s --check-prefix=DIS
+
+declare i16 @llvm.bswap.i16(i16)
+
+define internal i32 @testRev(i32 %a) {
+; ASM-LABEL:testRev:
+; DIS-LABEL:00000000 <testRev>:
+; IASM-LABEL:testRev:
+
+entry:
+; ASM-NEXT:.LtestRev$entry:
+; IASM-NEXT:.LtestRev$entry:
+
+  %a.arg_trunc = trunc i32 %a to i16
+  %v = tail call i16 @llvm.bswap.i16(i16 %a.arg_trunc)
+
+; ***** Example of rev instruction. *****
+; ASM-NEXT:     rev     r0, r0
+; DIS-NEXT:   0:        e6bf0f30
+; IASM-NEXT:    .byte 0x30
+; IASM-NEXT:    .byte 0xf
+; IASM-NEXT:    .byte 0xbf
+; IASM-NEXT:    .byte 0xe6
+
+; ASM-NEXT:     lsr     r0, r0, #16
+
+  %.ret_ext = zext i16 %v to i32
+  ret i32 %.ret_ext
+}