Fix nits in committed CL's for the integrated ARM assembler.

src/IceInstARM32.cpp

@@ -110,8 +110,12 @@ void InstARM32::emitUsingTextFixup(const Cfg *Func) const {
   emit(Func);
   Ctx->setStrEmit(OldStr);
   if (Ctx->getFlags().getDisableHybridAssembly()) {
-    llvm::errs() << "Can't assemble: " << StrBuf.str() << "\n";
-    UnimplementedError(Ctx->getFlags());
+    if (Ctx->getFlags().getSkipUnimplemented()) {
+      Asm->trap();
+    } else {
+      llvm::errs() << "Can't assemble: " << StrBuf.str() << "\n";
+      UnimplementedError(Ctx->getFlags());
+    }
     return;
   }
   Asm->emitTextInst(StrBuf.str(), Asm->getEmitTextSize());
@@ -1701,7 +1705,7 @@ template <> void InstARM32Vsqrt::emitIAS(const Cfg *Func) const {
     Asm->vsqrtd(Dest, getSrc(0), getPredicate());
     break;
   default:
-    llvm::report_fatal_error("Vqrt of non-floating type");
+    llvm::report_fatal_error("Vsqrt of non-floating type");
   }
   if (Asm->needsTextFixup())
     emitUsingTextFixup(Func);

tests_lit/assembler/arm32/trap.ll

 ; Show that we can translate IR instruction "trap".
 
-; Note: We use integer division to test this, since a trap is inserted
-; if one divides by zero.
-
 ; REQUIRES: allow_dump
 
 ; Compile using standalone assembler.
@@ -23,20 +20,36 @@
 ; RUN:   --args -Om1 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
+; testUnreachable generates a trap for the unreachable instruction.
+
+define internal void @testUnreachable() {
+; ASM-LABEL: testUnreachable:
+; DIS-LABEL: 00000000 <testUnreachable>:
+
+  unreachable
+
+; ASM:  .long 0xe7fedef0
+; DIS-NEXT:    0:       e7fedef0
+; IASM-NOT:     .long 0xe7fedef0
+}
+
+; testTrap uses integer division to test this, since a trap is
+; inserted if one divides by zero.
+
 define internal i32 @testTrap(i32 %v1, i32 %v2) {
 ; ASM-LABEL: testTrap:
-; DIS-LABEL: 00000000 <testTrap>:
+; DIS-LABEL: 00000010 <testTrap>:
 ; IASM-LABEL: testTrap:
 
   %res = udiv i32 %v1, %v2
 
 ; ASM:          bne
-; DIS:        18:	1a000000
+; DIS:  28:     1a000000
 ; IASM-NOT:     bne
 
 ; ASM-NEXT:     .long 0xe7fedef0
-; DIS-NEXT:   1c:	e7fedef0
-; IASM-NOT:     .long
+; DIS-NEXT:  2c:        e7fedef0
+; IASM-NOT:     .long 0xe7fedef0
 
   ret i32 %res
 }