Subzero. ARM32. Vector lowering. And.

src/IceInstARM32.cpp

@@ -621,6 +621,11 @@ template <> void InstARM32Vadd::emitIAS(const Cfg *Func) const {
   }
 }
 
+template <> void InstARM32Vand::emitIAS(const Cfg *Func) const {
+  // TODO(kschimpf): add support for these instructions
+  emitUsingTextFixup(Func);
+}
+
 template <> void InstARM32Vdiv::emitIAS(const Cfg *Func) const {
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   const Variable *Dest = getDest();
@@ -1029,6 +1034,7 @@ template <> const char *InstARM32Sub::Opcode = "sub";
 template <> const char *InstARM32Udiv::Opcode = "udiv";
 // FP
 template <> const char *InstARM32Vadd::Opcode = "vadd";
+template <> const char *InstARM32Vand::Opcode = "vand";
 template <> const char *InstARM32Vdiv::Opcode = "vdiv";
 template <> const char *InstARM32Veor::Opcode = "veor";
 template <> const char *InstARM32Vmla::Opcode = "vmla";

src/IceInstARM32.h

@@ -422,6 +422,7 @@ public:
     Uxt,
     Vabs,
     Vadd,
+    Vand,
     Vcmp,
     Vcvt,
     Vdiv,
@@ -918,6 +919,7 @@ using InstARM32Sdiv = InstARM32ThreeAddrGPR<InstARM32::Sdiv>;
 using InstARM32Sub = InstARM32ThreeAddrGPR<InstARM32::Sub>;
 using InstARM32Udiv = InstARM32ThreeAddrGPR<InstARM32::Udiv>;
 using InstARM32Vadd = InstARM32ThreeAddrFP<InstARM32::Vadd>;
+using InstARM32Vand = InstARM32ThreeAddrFP<InstARM32::Vand>;
 using InstARM32Vdiv = InstARM32ThreeAddrFP<InstARM32::Vdiv>;
 using InstARM32Veor = InstARM32ThreeAddrFP<InstARM32::Veor>;
 using InstARM32Vmla = InstARM32FourAddrFP<InstARM32::Vmla>;

src/IceTargetLoweringARM32.cpp

@@ -2807,6 +2807,7 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Instr) {
     case InstArithmetic::Add:
     case InstArithmetic::Fsub:
     case InstArithmetic::Sub:
+    case InstArithmetic::And:
       break;
     }
   }
@@ -2955,8 +2956,13 @@ void TargetARM32::lowerArithmetic(const InstArithmetic *Instr) {
       }
     }
     Variable *Src0R = Srcs.src0R(this);
-    Operand *Src1RF = Srcs.src1RF(this);
-    _and(T, Src0R, Src1RF);
+    if (isVectorType(DestTy)) {
+      Variable *Src1R = legalizeToReg(Src1);
+      _vand(T, Src0R, Src1R);
+    } else {
+      Operand *Src1RF = Srcs.src1RF(this);
+      _and(T, Src0R, Src1RF);
+    }
     _mov(Dest, T);
     return;
   }

src/IceTargetLoweringARM32.h

@@ -769,6 +769,9 @@ protected:
   void _vadd(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstARM32Vadd>(Dest, Src0, Src1);
   }
+  void _vand(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert<InstARM32Vand>(Dest, Src0, Src1);
+  }
   void _vcvt(Variable *Dest, Variable *Src, InstARM32Vcvt::VcvtVariant Variant,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Vcvt>(Dest, Src, Variant, Pred);

tests_lit/assembler/arm32/and-vec.ll

+; Show that we know how to translate vsub vector instructions.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
+; RUN:   | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 \
+; RUN:   | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
+; RUN:   | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN:   --args -O2 \
+; RUN:   | FileCheck %s --check-prefix=DIS
+
+define internal <4 x i32> @testVand4i32(<4 x i32> %v1, <4 x i32> %v2) {
+; ASM-LABEL: testVand4i32:
+; DIS-LABEL: 00000000 <testVand4i32>:
+; IASM-LABEL: testVand4i32:
+
+entry:
+  %res = and <4 x i32> %v1, %v2
+
+; ASM:     vand.i32        q0, q0, q1
+; DIS:   0:       f2000152
+; IASM:     vand.i32
+
+  ret <4 x i32> %res
+}
+
+define internal <8 x i16> @testVand8i16(<8 x i16> %v1, <8 x i16> %v2) {
+; ASM-LABEL: testVand8i16:
+; DIS-LABEL: 00000010 <testVand8i16>:
+; IASM-LABEL: testVand8i16:
+
+entry:
+  %res = and <8 x i16> %v1, %v2
+
+; ASM:     vand.i16        q0, q0, q1
+; DIS:   10:       f2000152
+; IASM:     vand.i16
+
+  ret <8 x i16> %res
+}
+
+define internal <16 x i8> @testVand16i8(<16 x i8> %v1, <16 x i8> %v2) {
+; ASM-LABEL: testVand16i8:
+; DIS-LABEL: 00000020 <testVand16i8>:
+; IASM-LABEL: testVand16i8:
+
+entry:
+  %res = and <16 x i8> %v1, %v2
+
+; ASM:     vand.i8        q0, q0, q1
+; DIS:   20:       f2000152
+; IASM:     vand.i8
+
+  ret <16 x i8> %res
+}
+
+;;
+;; The following tests make sure logical and works on predicate vectors.
+;;
+
+define internal <4 x i1> @testVand4i1(<4 x i1> %v1, <4 x i1> %v2) {
+; ASM-LABEL: testVand4i1:
+; DIS-LABEL: 00000030 <testVand4i1>:
+; IASM-LABEL: testVand4i1:
+
+entry:
+  %res = and <4 x i1> %v1, %v2
+
+; ASM:     vand.i32        q0, q0, q1
+; DIS:   30:       f2000152
+; IASM:     vand.i32
+
+  ret <4 x i1> %res
+}
+
+define internal <8 x i1> @testVand8i1(<8 x i1> %v1, <8 x i1> %v2) {
+; ASM-LABEL: testVand8i1:
+; DIS-LABEL: 00000040 <testVand8i1>:
+; IASM-LABEL: testVand8i1:
+
+entry:
+  %res = and <8 x i1> %v1, %v2
+
+; ASM:     vand.i16        q0, q0, q1
+; DIS:   40:       f2000152
+; IASM:     vand.i16
+
+  ret <8 x i1> %res
+}
+
+define internal <16 x i1> @testVand16i1(<16 x i1> %v1, <16 x i1> %v2) {
+; ASM-LABEL: testVand16i1:
+; DIS-LABEL: 00000050 <testVand16i1>:
+; IASM-LABEL: testVand16i1:
+
+entry:
+  %res = and <16 x i1> %v1, %v2
+
+; ASM:     vand.i8        q0, q0, q1
+; DIS:   50:       f2000152
+; IASM:     vand.i8
+
+  ret <16 x i1> %res
+}