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swiftshader
Commit c628b680 by John Porto
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Subzero. ARM32. Fixes register aliasing bugs.

BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076 R=kschimpf@google.com Review URL: https://codereview.chromium.org/1528413002 .
parent 2187c84a
Showing with 7 additions and 8 deletions
pydir/gen_arm32_reg_tables.py
...@@ -65,7 +65,7 @@ class Reg(object): ...@@ -65,7 +65,7 @@ class Reg(object):
Encode=self.Encode, Features=self.Features) Encode=self.Encode, Features=self.Features)
def IsAnAliasOf(self, Other): def IsAnAliasOf(self, Other):
return self.Name in self.Features.Aliases().Aliases return Other.Name in self.Features.Aliases().Aliases
# Note: The following tables break the usual 80-col on purpose -- it is easier # Note: The following tables break the usual 80-col on purpose -- it is easier
# to read the register tables if each register entry is contained on a single # to read the register tables if each register entry is contained on a single
...@@ -130,7 +130,7 @@ FP32 = [ ...@@ -130,7 +130,7 @@ FP32 = [
Reg('s28', 28, IsPreserved=1, IsFP32=1, Aliases='s28, d14, q7'), Reg('s28', 28, IsPreserved=1, IsFP32=1, Aliases='s28, d14, q7'),
Reg('s29', 29, IsPreserved=1, IsFP32=1, Aliases='s29, d14, q7'), Reg('s29', 29, IsPreserved=1, IsFP32=1, Aliases='s29, d14, q7'),
Reg('s30', 30, IsPreserved=1, IsFP32=1, Aliases='s30, d15, q7'), Reg('s30', 30, IsPreserved=1, IsFP32=1, Aliases='s30, d15, q7'),
Reg('s31', 31, IsPreserved=1, IsFP32=1, Aliases='s31, d14, q7'), Reg('s31', 31, IsPreserved=1, IsFP32=1, Aliases='s31, d15, q7'),
] ]
FP64 = [ FP64 = [
...@@ -145,10 +145,10 @@ FP64 = [ ...@@ -145,10 +145,10 @@ FP64 = [
Reg( 'd8', 8, IsPreserved=1, IsFP64=1, Aliases= 'd8, q4, s16, s17'), Reg( 'd8', 8, IsPreserved=1, IsFP64=1, Aliases= 'd8, q4, s16, s17'),
Reg( 'd9', 9, IsPreserved=1, IsFP64=1, Aliases= 'd9, q4, s18, s19'), Reg( 'd9', 9, IsPreserved=1, IsFP64=1, Aliases= 'd9, q4, s18, s19'),
Reg('d10', 10, IsPreserved=1, IsFP64=1, Aliases='d10, q5, s20, s21'), Reg('d10', 10, IsPreserved=1, IsFP64=1, Aliases='d10, q5, s20, s21'),
Reg('d11', 11, IsPreserved=1, IsFP64=1, Aliases='d11, q5, s22, s24'), Reg('d11', 11, IsPreserved=1, IsFP64=1, Aliases='d11, q5, s22, s23'),
Reg('d12', 12, IsPreserved=1, IsFP64=1, Aliases='d12, q6, s24, s25'), Reg('d12', 12, IsPreserved=1, IsFP64=1, Aliases='d12, q6, s24, s25'),
Reg('d13', 13, IsPreserved=1, IsFP64=1, Aliases='d13, q6, s26, s27'), Reg('d13', 13, IsPreserved=1, IsFP64=1, Aliases='d13, q6, s26, s27'),
Reg('d14', 14, IsPreserved=1, IsFP64=1, Aliases='d14, q7, s28, s28'), Reg('d14', 14, IsPreserved=1, IsFP64=1, Aliases='d14, q7, s28, s29'),
Reg('d15', 15, IsPreserved=1, IsFP64=1, Aliases='d15, q7, s30, s31'), Reg('d15', 15, IsPreserved=1, IsFP64=1, Aliases='d15, q7, s30, s31'),
Reg('d16', 16, IsScratch=1, IsFP64=1, Aliases='d16, q8'), Reg('d16', 16, IsScratch=1, IsFP64=1, Aliases='d16, q8'),
Reg('d17', 17, IsScratch=1, IsFP64=1, Aliases='d17, q8'), Reg('d17', 17, IsScratch=1, IsFP64=1, Aliases='d17, q8'),
...@@ -203,7 +203,6 @@ for _, RegClass in RegClasses: ...@@ -203,7 +203,6 @@ for _, RegClass in RegClasses:
for Reg in RegClass: for Reg in RegClass:
for Alias in AllRegs[Reg.Name].Features.Aliases().Aliases: for Alias in AllRegs[Reg.Name].Features.Aliases().Aliases:
assert AllRegs[Alias].IsAnAliasOf(Reg), '%s VS %s' % (Reg, AllRegs[Alias]) assert AllRegs[Alias].IsAnAliasOf(Reg), '%s VS %s' % (Reg, AllRegs[Alias])
assert AllRegs[Alias].IsAnAliasOf(Reg), '%s VS %s' % (Reg, AllRegs[Alias])
assert (AllRegs[Alias].Features.LivesInGPR() == assert (AllRegs[Alias].Features.LivesInGPR() ==
Reg.Features.LivesInGPR()), '%s VS %s' % (Reg, AllRegs[Alias]) Reg.Features.LivesInGPR()), '%s VS %s' % (Reg, AllRegs[Alias])
assert (AllRegs[Alias].Features.LivesInVFP() == assert (AllRegs[Alias].Features.LivesInVFP() ==
......
src/IceRegistersARM32.def
...@@ -62,7 +62,7 @@ ...@@ -62,7 +62,7 @@
X(Reg_s28, 28, "s28", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s28, d14, q7)) \ X(Reg_s28, 28, "s28", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s28, d14, q7)) \
X(Reg_s29, 29, "s29", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s29, d14, q7)) \ X(Reg_s29, 29, "s29", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s29, d14, q7)) \
X(Reg_s30, 30, "s30", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s30, d15, q7)) \ X(Reg_s30, 30, "s30", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s30, d15, q7)) \
X(Reg_s31, 31, "s31", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s31, d14, q7)) X(Reg_s31, 31, "s31", 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, REGLIST3(RegARM32, s31, d15, q7))
#define REGARM32_FP64_TABLE \ #define REGARM32_FP64_TABLE \
X(Reg_d31, 31, "d31", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d31, q15)) \ X(Reg_d31, 31, "d31", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d31, q15)) \
...@@ -82,10 +82,10 @@ ...@@ -82,10 +82,10 @@
X(Reg_d17, 17, "d17", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d17, q8)) \ X(Reg_d17, 17, "d17", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d17, q8)) \
X(Reg_d16, 16, "d16", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d16, q8)) \ X(Reg_d16, 16, "d16", 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, REGLIST2(RegARM32, d16, q8)) \
X(Reg_d15, 15, "d15", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d15, q7, s30, s31)) \ X(Reg_d15, 15, "d15", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d15, q7, s30, s31)) \
X(Reg_d14, 14, "d14", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d14, q7, s28, s28)) \ X(Reg_d14, 14, "d14", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d14, q7, s28, s29)) \
X(Reg_d13, 13, "d13", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d13, q6, s26, s27)) \ X(Reg_d13, 13, "d13", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d13, q6, s26, s27)) \
X(Reg_d12, 12, "d12", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d12, q6, s24, s25)) \ X(Reg_d12, 12, "d12", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d12, q6, s24, s25)) \
X(Reg_d11, 11, "d11", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d11, q5, s22, s24)) \ X(Reg_d11, 11, "d11", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d11, q5, s22, s23)) \
X(Reg_d10, 10, "d10", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d10, q5, s20, s21)) \ X(Reg_d10, 10, "d10", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d10, q5, s20, s21)) \
X(Reg_d9, 9, "d9", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d9, q4, s18, s19)) \ X(Reg_d9, 9, "d9", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d9, q4, s18, s19)) \
X(Reg_d8, 8, "d8", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d8, q4, s16, s17)) \ X(Reg_d8, 8, "d8", 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, REGLIST4(RegARM32, d8, q4, s16, s17)) \
......
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