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  1. 20 Nov, 2015 1 commit
  3. 19 Nov, 2015 2 commits
  5. 18 Nov, 2015 2 commits
  7. 17 Nov, 2015 8 commits
  9. 16 Nov, 2015 3 commits
  11. 14 Nov, 2015 2 commits
  13. 13 Nov, 2015 2 commits
    • Subzero: Find rematerializable variables transitively. · 3607b6c9
      Jim Stichnoth authored 
      There are situations where a variable is assigned as the result of a rematerializable alloca instruction, and then another variable is assigned as essentially a known-offset interior pointer into the alloca space.  In this case, the secondary variable is also rematerializable.

We add a pass, after alloca analysis, to find these derived variables and mark them transitively as rematerializable.  Because we lack use-def chains (or in fact any map to variable use locations), we need to iterate over the CFG until convergence.  Fortunately, this is pretty cheap, and not even done unless the alloca analysis seeds it with an initial set of rematerializable variables.

This analysis is only really needed for arithmetic instructions, but we also need to apply it to assignments and pointer-type bitcasts that are added when the IceConverter directly parses a .ll file rather than a .pexe file.

BUG= none
R=jpp@chromium.org, sehr@chromium.org

Review URL: https://codereview.chromium.org/1441793002 .
    • Subzero: Use "pxor reg,reg" to load a floating-point scalar 0.0 value. · 99165667
      Jim Stichnoth authored 
      BUG= none
R=jpp@chromium.org, sehr@chromium.org

Review URL: https://codereview.chromium.org/1439363002 .
  15. 12 Nov, 2015 4 commits
  17. 11 Nov, 2015 7 commits
  19. 10 Nov, 2015 4 commits
  21. 09 Nov, 2015 5 commits
    • Subzero. ARM32. Address mode formation. · f5f02f7e
      John Porto authored 
      BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076
R=kschimpf@google.com, stichnot@chromium.org

Review URL: https://codereview.chromium.org/1422753010 .
    • Add UMULL to ARM integrated assembler. · 430e8447
      Karl Schimpf authored 
      Also formatted IceCfg.cpp, since it needed it.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1422253003 .
    • Fixes LDR and STR instructions. Two types of mistakes were being made. · b9f27229
      Karl Schimpf authored 
      First, the width was not being correctly defined for non-vector
instructions.

Second, the order of the width/condition was incorrect when the
instruction was prefixed with a V. That is, for V prefixed instructions,
the order is predicate/width while for non-V prefixed instructions the
order is width/predicate.

Also fixes bug in target lowering that did not always convert results
of a compare to i1.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1415953007 .
    • Subzero: Refactor x86 register representation to actively use aliases. · c59288b3
      Jim Stichnoth authored 
      Sets up additional register attributes, plus the notion of register classes, to enable robust usage of the high 8-bit GPRs (ah/bh/ch/dh), for both x86-32 and x86-64.  (Note that the x86-64 changes are currently untested.)

We add a Register Class field to the Variable class.  The default register class is a value corresponding to the variable's type, but the target can extend the set of register class values, and the target lowering can assign different register classes as needed.  The register allocator uses the register class instead of the type to determine the set of registers to draw from.

For x86-64, the high 8-bit registers are not included in the general register allocation pool, but there are explicit references to ah for lowering the div/rem instructions.

The target lowering is modified as needed to make sure types are appropriate and register use in instructions is legalized.

Some other fixes and cleanups are included in this CL:

* Makefile.standalone changes.  Source files are reordered so that the more expensive compiles are done earlier, speeding up parallel builds by decreasing fragmentation.  A dependency error is fixed for check-spec.

* A bug is fixed in advanced phi lowering.  When a temporary is introduced to break a cycle, we were neglecting to updated the predecessor count for one of the operands, leading to an assertion failure.  (Applying that fix to master resulted in no changes to spec2k code generation.)  A consistency check is added to help find future problems like this.  Also, refactored iteration over the Phi descriptor array to use range-based for loops and avoid directly indexing the array.

* Removed most of the "IceType_" prefixes in x-macro tables for brevity.

* Fix a correctness TODO in the register allocator.  This had no effect on spec2k code generation in master or in this CL, so we were probably just lucky.

* Made some much-needed s/Dest->getType()/Ty/ changes for brevity, in the target lowering sections that needed other changes.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4095
R=jpp@chromium.org

Review URL: https://codereview.chromium.org/1427973003 .
    • Subzero: Fix a bug in advanced phi lowering. · ea15bbe7
      Jim Stichnoth authored 
      When a temporary is introduced to break a cycle, we neglected to update the predecessor count for one of the operands, leading to a possible assertion failure.

This problem isn't currently seen in master, but it arises when we enable register aliases, as in https://codereview.chromium.org/1427973003/ .  No changes are seen in spec2k code generation as a result of this fix.

A consistency check is added to help find future problems like this.

Also, refactored iteration over the Phi descriptor array to use range-based for loops and avoid directly indexing the array.

BUG= none
R=jpp@chromium.org

Review URL: https://codereview.chromium.org/1435543002 .