- 25 Feb, 2016 2 commits
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Jim Stichnoth authored
See failed build at https://build.chromium.org/p/tryserver.nacl/builders/nacl-toolchain-win7-pnacl-x86_64/builds/3441 . BUG= none TBR=jpp@chromium.org Review URL: https://codereview.chromium.org/1732233002 .
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Jim Stichnoth authored
Instead of "./pnacl-sz <args>", one can run: ../../../run.py ./pnacl-sz.x8632.nexe <args> or ../../../run.py ./pnacl-sz.x8664.nexe <args> Hopefully the translator performance characteristics are close to that of the browser hookup. Adds sb builds to two of the presubmit configurations. BUG= none R=jpp@chromium.org Review URL: https://codereview.chromium.org/1738633002 .
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- 24 Feb, 2016 3 commits
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John Porto authored
Introduces Ice::SmallBitVector. Modifies ConstantRelocatables so that known offsets (i.e., not offsets to the code stream) do no require GlobalContext allocations. Modifies Cfg-local containers to use the CfgLocalAllocator. BUG= R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1738443002 .
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Jim Stichnoth authored
TBR=jpp@chromium.org BUG= none Review URL: https://codereview.chromium.org/1730263002 .
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Reed Kotler authored
This is part of ARM patch: https://codereview.chromium.org/1151663004/ BUG= R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1724643002 . Patch from Reed Kotler <rkotlerimgtec@gmail.com>.
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- 20 Feb, 2016 1 commit
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Reed Kotler authored
Implement 64 bit multiply in mips32 and, in addition, add the lo/hi registers which are also used for other 64 bit math such as div, rem. BUG= R=jpp@chromium.org, stichnot@chromium.org Review URL: https://codereview.chromium.org/1716483003 . Patch from Reed Kotler <rkotlerimgtec@gmail.com>.
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- 18 Feb, 2016 1 commit
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John Porto authored
BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076 R=eholk@chromium.org, stichnot@chromium.org Review URL: https://codereview.chromium.org/1708753002 .
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- 17 Feb, 2016 7 commits
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Eric Holk authored
This removes most of the #ifndef ARM32 directives so we get more thorough testing. It still uses fewer iterations due to running on Qemu, but I did manually check to be sure that the tests pass without any special casing at all. BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076 R=jpp@chromium.org, kschimpf@google.com Review URL: https://codereview.chromium.org/1708903002 .
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Eric Holk authored
BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1685253003 .
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Eric Holk authored
With this change, we pass the select crosstest. Since this would have introduced a three-argument version of scalarizeInstruction, I decided to generalize it using templates. BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1683243003 .
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John Porto authored
X8664_STACK_HACK was an intrusive way to get the crosstests to run while x32 support was not implemented in llvm. The hack is longer needed. R=eholk@chromium.org Review URL: https://codereview.chromium.org/1706883003 .
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Karl Schimpf authored
BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334 R=eholk@chromium.org, stichnot@chromium.org Review URL: https://codereview.chromium.org/1697263007 .
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Reed Kotler authored
It's troublesome that we have to type (this) in several places but I don't see a away around it yet and it does not add to the line of code count at all to have to do this; it's just not aesthetic to me. If this idea is okay, I can make all the similar changes in the Mips Subzero port. BUG= Review URL: https://codereview.chromium.org/1661233002 . Patch from Reed Kotler <rkotlerimgtec@gmail.com>.
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John Porto authored
BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1409863006 .
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- 16 Feb, 2016 2 commits
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Jim Stichnoth authored
The original implementation hard-coded the target to x86-32. The new implementation mirrors pnacl-llc by probing the architecture it is running on. Continues the plumbing work in https://codereview.chromium.org/1698523003/ , toward the goal of enabling sandboxed translator tests for x86-64, particularly on the spec bots. BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4077 R=jpp@chromium.org Review URL: https://codereview.chromium.org/1696123003 .
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Reed Kotler authored
There are many occurrences of if (RegNum == RegNumT::NoRegister). This patch eliminates NoRegister and provides a simpler mechanism for declaring and testing RegNumT values to see if they are undefined. BUG= none R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1691193002 . Patch from Reed Kotler <rkotlerimgtec@gmail.com>.
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- 11 Feb, 2016 1 commit
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Karl Schimpf authored
Implements a vector move as a vector orr on the corresponding Q registers. BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334 R=eholk@chromium.org Review URL: https://codereview.chromium.org/1694533002 .
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- 10 Feb, 2016 8 commits
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John Porto authored
Adds nonsfi support to the ARM32 backend. BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1665263003 .
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Karl Schimpf authored
Adds class name for the "QtoS" register class. BUG=None R=eholk@chromium.org Review URL: https://codereview.chromium.org/1687163002 .
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Karl Schimpf authored
BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334 R=jpp@chromium.org Review URL: https://codereview.chromium.org/1679023008 .
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Eric Holk authored
This is part of a sequence of patches to quickly fill out vector support by scalarizing the remaining operations. Later we can work to generate better code. BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1683153003 .
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Jim Stichnoth authored
Originally, register numbers were represented explicitly as int32_t, particularly so that -1 (or negative values in general) could be used as a NoRegister sentinel value. This created two problems: 1. It would be better to use a unique name for the type, to distinguish from other explicit int32_t uses such as stack offsets. 2. Apart from NoRegister, register number values ultimately come from unsigned sources like enum values and bitvector positions. This results in a number of clumsy casts to remove compiler warnings. This creates a simple RegNumT class to manage this. It also deletes ordered comparison operators to help catch errors where particular register number orderings are assumed (as opposed to orderings of the encoded register values). In addition, it creates a RegNumBitVector wrapper class that makes it much cleaner to do range-based for loops over bit vectors that represent RegNumT sets. BUG= none R=eholk@chromium.org, jpp@chromium.org Review URL: https://codereview.chromium.org/1676123002 .
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Karl Schimpf authored
CL https://codereview.chromium.org/1687553002 introduced a bug when running: make -f Makefile.standalone check-lit FORCEASM=1 The cause of the problem is the way options "--asemble --disassemble" work in run-pnacl-sz.py. When compiling using "--filetype=asm", the assembler writes: .word 0xe7fedef0 The output after assembly/disassembly is the same as above. On the other hand, when compiling using "--filetype=iasm", the assembler writes: .byte 0xe7 .byte 0xfe .byte 0xde .byte 0xf0 While the same sequence of bytes is assembled, the dissassembly for the latter generates assembly instruction: udf #60896 ; 0xede0 The fix is to not check the generated disassembled instructions. Rather, have it check if the same word is associated with the assembly instruction. Longer term, we should fix the several different ways --filetype=asm introduces this instruction to match the "udf ..." output. BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1682253003 .
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Eric Holk authored
Enables vector division by scalarization. Also, removed an assert as suggested by Karl in a previous CL: https://codereview.chromium.org/1646033002/diff/1/src/IceInstARM32.cpp#newcode717 BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1681003002 .
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Jim Stichnoth authored
To view the non-whitespace changes in this CL: git cl patch -b testbranch 1678133003 git diff -w --ignore-blank-lines -b master Such changes are only in gen_arm32_reg_tables.py and IceInst.cpp. There are lots of tab characters in .ll files that shouldn't be there, but fixing them would require some thought about how to do consistent formatting, so that's left for later. BUG= none R=eholk@chromium.org, kschimpf@google.com Review URL: https://codereview.chromium.org/1678133003 .
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- 09 Feb, 2016 3 commits
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Karl Schimpf authored
This is done by putting far pointers (for calls) into a register and then do an indirect call. This was done to guarantee that we aren't putting a size limit on ARM32 executables. BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076 R=jpp@chromium.org Review URL: https://codereview.chromium.org/1687553002 .
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Karl Schimpf authored
This change allows pnacl-sz to randomly insert NOPs into the generated code, as is already done with X86. BUG=None R=eholk@chromium.org, stichnot@chromium.org Review URL: https://codereview.chromium.org/1670413002 .
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Karl Schimpf authored
BUG=None R=jpp@chromium.org, stichnot@chromium.org Review URL: https://codereview.chromium.org/1669973002 .
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- 08 Feb, 2016 1 commit
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Eric Holk authored
BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1655313002 .
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- 07 Feb, 2016 1 commit
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Jim Stichnoth authored
Some casts to size_t for use as array indexes are simply unnecessary. Some explicit declaration types are changed to "auto" to avoid redundancy with the static_cast type. A few llvm::dyn_cast<> operations are changed to llvm::cast<>, and vice versa. A few explicit declaration types are changed to "auto" when used with llvm::cast<> and llvm::dynamic_cast<>. Some of these were missed during an earlier cleansing because of multi-line issues. There are still a few opportunities related to Variable register numbers, but they are ignored for now because they are being addressed in another CL. BUG= none R=jpp@chromium.org Review URL: https://codereview.chromium.org/1674033002 .
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- 05 Feb, 2016 4 commits
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Jim Stichnoth authored
The low-level mul instruction may produce results in a register pair where one register is the explicit dest of the instruction, and the other register is defined through a FakeDef. If the FakeDef portion is ultimately unused, the FakeDef gets dead-code eliminated, and the register allocator doesn't know that the mul instruction affects the other register. On x86, this can silently produce incorrect code. On ARM, the emitter complains that the explicitly represented second dest variable does not have a register. The fix is to add a FakeUse of the FakeDef'd register. Unfortunately, this prevents the low-level mul instruction from ever being dead-code eliminated, but that's probably OK because it should have been eliminated at the high level. BUG= none R=eholk@chromium.org Review URL: https://codereview.chromium.org/1678523002 .
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Jim Stichnoth authored
Add the variable name and function name to the fatal error message. BUG= none R=kschimpf@google.com Review URL: https://codereview.chromium.org/1677593003 .
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Jim Stichnoth authored
In the beginning, Ice::Inst was called IceInst, and patterns like "IceInst *Inst = ..." made perfect sense. After the Ice:: name change, "Inst *Inst = ..." continued to compile, mostly. However, shadowing a type name is clumsy and newer code tends to use "Inst *Instr", so we might as well switch all the instances over. Some are still called "I" and those are left alone. BUG= none R=kschimpf@google.com Review URL: https://codereview.chromium.org/1665423002 .
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Karl Schimpf authored
Flattens out MOV's emitIAS methods making it easier to see valid types for source/destination of the move. BUG=None R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1665323002 .
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- 04 Feb, 2016 4 commits
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Karl Schimpf authored
Fixes emit() methods for load/store to specify the element size (affects alignment issues). Also adds assembler methods to generate the corresponding binary forms, and updates emitIAS() to call these assembler methods. BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1663053008 .
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John Porto authored
This CL modifies the ELF emission so the addends are calculated during object file creation, and not during function code emission. BUG= R=kschimpf@google.com, stichnot@chromium.org Review URL: https://codereview.chromium.org/1669443002 .
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John Porto authored
The AutoMemorySandboxer does not have to emit a bundle lock/unlock pair for memory operations in x8632, but the current does emit it. This CL changes this behavior. BUG= R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1661403002 .
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John Porto authored
BUG= R=kschimpf@google.com, stichnot@chromium.org Review URL: https://codereview.chromium.org/1661193004 .
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- 03 Feb, 2016 2 commits
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Reed Kotler authored
Following the newer convention enhances readability and in addition this is a prelude to some macro changes in unimplemented I would like to make in order to simplify that code. BUG= R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1667553002 . Patch from Reed Kotler <rkotlerimgtec@gmail.com>.
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Karl Schimpf authored
BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334 R=stichnot@chromium.org Review URL: https://codereview.chromium.org/1665593002 .
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