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  1. 05 Nov, 2015 2 commits
    • Fix ARM emit() methods to count instructions generated. · 856734ca
      Karl Schimpf authored 
      Previously, the code assumed that the emit() method of all ARM
instructions emitted a single instruction. This is false. Instructions
like PUSH and POP may generate multiple instructions.

This is only a problem when the hybrid ARM assembler reverts back to
using the stand-alone assembler to generate instructions the
integrated assembler can't handle.

The fix is to add infrastructure to allow ARM instructions to
communicate to the assembler, the number of instructions they
generate, so that the correct-sized filler is added to the assembly
buffer.

This fixes all cross-test failures for (pc-relative) branches, except
one.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1426513004 .
    • Subzero: Refactor some common TargetLowering initializations. · 94844f12
      Jim Stichnoth authored 
      Each TargetLowering subclass has several fields (generally register allocation related) that are initialized to the same values every time a TargetLowering object is created.  These fields are essentially const once initialized, so there is no reason to repeatedly initialize them.

The solution is to make them static fields, and statically initialize them at program startup.

This also makes it practical to access such fields without needing a TargetLowering object.

There are likely more items that should also get this treatment, but those can be changed later.

The staticInit() method needs a run-once guard because the unit tests actually cause it to be called more than once.

BUG= none
R=kschimpf@google.com

Review URL: https://codereview.chromium.org/1418853005 .
  3. 04 Nov, 2015 5 commits
  5. 02 Nov, 2015 2 commits
  7. 31 Oct, 2015 1 commit
  9. 30 Oct, 2015 12 commits
  11. 29 Oct, 2015 3 commits
  13. 28 Oct, 2015 2 commits
    • Sets the stage for enabling the use of the 8-bit high registers, but doesn't yet… · 5bff61c4
      Jim Stichnoth authored 
      Sets the stage for enabling the use of the 8-bit high registers, but doesn't yet turn it on because more work is needed for correctness.

In the lowering, typing is tightened up so that we don't specify e.g. eax when we really mean ax or al.  This gets rid of the ShiftHack hack.  The one exception is the pinsr instruction which always requires an r32 register even if the memory operand is m8 or m16.

The x86 assembler unit tests are fixed, by not passing a GlobalContext arg to the Assembler ctor.

Many constexpr and "auto *" upgrades are applied.  Sorry for not putting this into a separate CL - a few local fixes got out of hand...

Tested in the following ways:
- "make check-lit" - some .ll CHECK line changes due to register randomization
- "make check-xtest"
- "make check-xtest" with forced filetype=asm (via local .py hack)
- spec2k with all -filetype options
- compare before-and-after spec2k filetype=asm output - a few differences where the correct narrow register is used instead of the full-width register

To do in the next CL:

1. Add new register classes:
  (a) 32-bit GPR truncable to 8-bit (eax, ecx, edx, ebx)
  (b) 16-bit GPR truncable to 8-bit (ax, cx, dx, bx)
  (c) 8-bit truncable from 16/32-bit (al, bl, cl, dl)
  (c) 8-bit "mov"able from ah/bh/ch/dh

2. Enable use of ah/bh/ch/dh for x86-32.

3. Enable use of ah (but skip bh/ch/dh) for x86-64.

4. Statically initialize register tables in the TargetLowering subclass.

BUG= none
R=jpp@chromium.org, kschimpf@google.com

Review URL: https://codereview.chromium.org/1419903002 .
    • Subzero. ARM32. Implements the Availability Optimization. · 562233c8
      John Porto authored 
      Implements the Availability optimization:

a = b
x = f(a, c)

becomes

a = b
x = f(b, c)

This only triggers if b is an infinite-weight temporary, and it
prevents a potential spill at the cost of higher register pressure.

BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1424873003 .
  15. 27 Oct, 2015 5 commits
  17. 23 Oct, 2015 1 commit
  19. 22 Oct, 2015 1 commit
  21. 21 Oct, 2015 1 commit
  23. 17 Oct, 2015 1 commit
  25. 16 Oct, 2015 4 commits