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  1. 31 Oct, 2015 1 commit
  3. 30 Oct, 2015 12 commits
  5. 29 Oct, 2015 3 commits
  7. 28 Oct, 2015 2 commits
    • Sets the stage for enabling the use of the 8-bit high registers, but doesn't yet… · 5bff61c4
      Jim Stichnoth authored 
      Sets the stage for enabling the use of the 8-bit high registers, but doesn't yet turn it on because more work is needed for correctness.

In the lowering, typing is tightened up so that we don't specify e.g. eax when we really mean ax or al.  This gets rid of the ShiftHack hack.  The one exception is the pinsr instruction which always requires an r32 register even if the memory operand is m8 or m16.

The x86 assembler unit tests are fixed, by not passing a GlobalContext arg to the Assembler ctor.

Many constexpr and "auto *" upgrades are applied.  Sorry for not putting this into a separate CL - a few local fixes got out of hand...

Tested in the following ways:
- "make check-lit" - some .ll CHECK line changes due to register randomization
- "make check-xtest"
- "make check-xtest" with forced filetype=asm (via local .py hack)
- spec2k with all -filetype options
- compare before-and-after spec2k filetype=asm output - a few differences where the correct narrow register is used instead of the full-width register

To do in the next CL:

1. Add new register classes:
  (a) 32-bit GPR truncable to 8-bit (eax, ecx, edx, ebx)
  (b) 16-bit GPR truncable to 8-bit (ax, cx, dx, bx)
  (c) 8-bit truncable from 16/32-bit (al, bl, cl, dl)
  (c) 8-bit "mov"able from ah/bh/ch/dh

2. Enable use of ah/bh/ch/dh for x86-32.

3. Enable use of ah (but skip bh/ch/dh) for x86-64.

4. Statically initialize register tables in the TargetLowering subclass.

BUG= none
R=jpp@chromium.org, kschimpf@google.com

Review URL: https://codereview.chromium.org/1419903002 .
    • Subzero. ARM32. Implements the Availability Optimization. · 562233c8
      John Porto authored 
      Implements the Availability optimization:

a = b
x = f(a, c)

becomes

a = b
x = f(b, c)

This only triggers if b is an infinite-weight temporary, and it
prevents a potential spill at the cost of higher register pressure.

BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1424873003 .
  9. 27 Oct, 2015 5 commits
  11. 23 Oct, 2015 1 commit
  13. 22 Oct, 2015 1 commit
  15. 21 Oct, 2015 1 commit
  17. 17 Oct, 2015 1 commit
  19. 16 Oct, 2015 5 commits
  21. 15 Oct, 2015 2 commits
    • Subzero: Various fixes in preparation for x86-32 register aliasing. · 1fb030c6
      Jim Stichnoth authored 
      1. Helper function sameVarOrReg() also needs to return true if the two physical registers alias or overlap.  Otherwise advanced phi lowering may pick an incorrect ordering.

2. With -asm-verbose, redundant truncation assignments expressed as _mov instructions, like "mov cl, ecx", need to have their register use counts updated properly, so that the LIVEEND= annotations are correct.

3. The register allocator should consider suitably typed aliases when choosing a register preference.

4. When evicting a variable, the register allocator should decrement the use count of all aliases.

5. When saving/restoring callee-save registers in the prolog/epilog, map each register to its "canonical" register (e.g. %bl --> %ebx) and make sure each canonical register is only considered once.

6. Remove some unnecessary Variable::setMustHaveReg() calls.

7. When assigning bool results as a constant 0 or 1, use an 8-bit constant instead of 32-bit so that only the 8-bit register gets assigned.

BUG= none
TEST= make check, plus spec2k -asm-verbose output is unchanged
R=kschimpf@google.com

Review URL: https://codereview.chromium.org/1405643003 .
    • Optimize 64-bit compares with zero · 5c87542a
      David Sehr authored 
      Comparisons with zero can be done with no branches in most cases and with
simpler sequences of operations.

BUG=
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1406593003 .
  23. 14 Oct, 2015 1 commit
  25. 13 Oct, 2015 2 commits
  27. 12 Oct, 2015 1 commit
    • Subzero: Consider all instruction variables for register preference. · 28b71be4
      Jim Stichnoth authored 
      The original code only looked at top-level source operands in the defining instruction, with a TODO to instead consider all inner variables in the instruction.

The primary reason is so that we end up with more instructions like
  mov eax, eax
which are later elided as redundant assignments.

A secondary reason is to foster more instructions like:
  mov ecx, [ecx]
rather than
  mov eax, [ecx]
where ecx's live range ends.  This hopefully keeps eax (in the latter case) free for longer and maybe allow some other variable to get a register.  By considering all instruction variables, we enable this.

BUG= none
R=jpp@chromium.org

Review URL: https://codereview.chromium.org/1392383003 .
  29. 09 Oct, 2015 2 commits