BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076
R=jpp@chromium.org, kschimpf@google.com

Review URL: https://codereview.chromium.org/1637173002 .

This CL also changes UnimplementedLoweringError to display the name of
the unimplemented instruction.

Improve test coverage for ARM32 vector load instructions.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076
R=jpp@chromium.org, kschimpf@google.com

Review URL: https://codereview.chromium.org/1639923002 .

These were all pointed out by the llvm test suite, the gcc torture
tests, and the scons tests.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4077
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1631383002 .

BUG=
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1574883002 .

Patch from Reed Kotler <rkotlerimgtec@gmail.com>.

Fixes case where IceTargetLowring.cpp and IceInstARM32.cpp generate
implementations for emitIAS().

BUG=None
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1638123002 .

Adds the scalar floating point versions of instruction VMLA to the
integrated ARM assembler.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=jpp@chromium.org, stichnot@chromium.org

Review URL: https://codereview.chromium.org/1634913005 .

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4077
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1616103002 .

Adds the vmovs/vmovd instructions to the integerated ARM assembler.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1624383004 .

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076
R=jpp@chromium.org

Review URL: https://codereview.chromium.org/1635713002 .

Cleans up the integrated ARM assembler, and its handling of register
memory addresses that can be modified by an immediate value. Handles
each possible encoding of such memory addresses.

Also adds assertions to check that the immediate value has the proper
range for the immediate value, based on the corresponding encoding.

BUG=None
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1630863002 .

Moves "EnsureCapacity Buffer" declarations inside emitInst(), so that
all callers need not add the declaration before calling emitInst().

BUG=None
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1636513002 .

Note: Only adds the APSR_nzcv register form of the instruction.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1636473002 .

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076
R=jpp@chromium.org

Review URL: https://codereview.chromium.org/1615613002 .

Also adds VMOVSR instruction to the integrated ARM assembler.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=jpp@chromium.org, stichnot@chromium.org

Review URL: https://codereview.chromium.org/1596613002 .

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1623433004 .

The main feature here is that when listing a register via the -reg-use or -reg-exclude option, we can limit the effect to a single register class, instead of applying it across all register classes.  Example:

  pnacl-sz -reg-use i32:eax,i32:ecx,i32:edx -reg-exclude f32:xmm0

Note that without the register class prefix, behavior is the same as before, specifically that the restriction applies to all register classes.

This requires a few high-level changes:

1. We need a mechanism to name *all* register classes, not just the standard ones that map to IceType values.

2. While we're at it, give standard types a more usable name, e.g. "v4i32" instead of "<4 x i32>".

3. Since we've commandeered ":" as the class/register token separator, we change ARM i64 register pair names from e.g. "r0:r1" to "r0r1".

The motivation is that for register allocator torture testing, we'd like to drastically restrict the registers available to e.g. the extensively-used i32 register class, while not overly restricting the seldom-used i32to8 register class (which reflects the set of i32 registers that may trivially truncate to i8).

BUG= none
R=kschimpf@google.com

Review URL: https://codereview.chromium.org/1614273002 .

A previous patch fixed vldrd/vstrd by dividing the immediate offset of
the instruction by 4 before encoding. This does the same for
vldrs/vstrs. It fixes the remaining problems with compiling spec2k
using -filetype=iasm.

It also fixes a minor bug in the divsion by 4, in the case that the
immediate value is negative.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=jpp@chromium.org

Review URL: https://codereview.chromium.org/1617993005 .

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=jpp@chromium.org, stichnot@chromium.org

Review URL: https://codereview.chromium.org/1611293003 .

Fixes the ARM integrated assembler by dividing the immediate offset
of the instruction by 4 before encoding.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=jpp@chromium.org, stichnot@chromium.org

Review URL: https://codereview.chromium.org/1619703008 .

Refactors the Address Mode optimization interface.

BUG=
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1605103002 .

BUG=
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1616673004 .

i.e.make -f Makefile.standalone check-lit CHECK_LIT_TESTS=tests_lit/llvm2ice_tests/arith.lll

The default will be for the directory to be in subzero but
it's also possible to create an absolute pathname.

Extended this to work with cross tests.

Added some primitive help for the makefile.

make -f Makefile.standalone help
make -f Makefile.standalone help-check-lit
make -f makefile.standalone help-check-xtest

BUG=
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1582243005 .

Patch from Reed Kotler <rkotlerimgtec@gmail.com>.

BUG=
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1571883002 .

Patch from Reed Kotler <rkotlerimgtec@gmail.com>.

BUG=
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1590403005 .

Patch from Reed Kotler <rkotlerimgtec@gmail.com>.

BUG= none
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1604063002 .

Patch from Reed Kotler <rkotlerimgtec@gmail.com>.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1604043005 .

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1603893003 .

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1601103010 .

BUG=
R=jpp@chromium.org

Review URL: https://codereview.chromium.org/1616483003 .

With the --force option, the behavior of its default setting is dangerous.  Specifically, it doesn't retranslate by default when you change the szbuild command-line arguments.  This leads to debugging frustration.

Therefore, we change the default setting to be "dumb" and always retranslate.

For bisection debugging, the user will quickly realize that they want to add "--force=0".

BUG= none
R=jpp@chromium.org

Review URL: https://codereview.chromium.org/1608323002 .

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4077
R=sehr@chromium.org

Review URL: https://codereview.chromium.org/1614453002 .

BUG=
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1606383002 .

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076
R=kschimpf@google.com, sehr@chromium.org, stichnot@chromium.org

Review URL: https://codereview.chromium.org/1609753002 .

BUG=
R=jpp@chromium.org, stichnot@chromium.org

Review URL: https://codereview.chromium.org/1592033002 .

These static members of the various TargetLowering classes are no longer used anywhere and can therefore be removed.

BUG= none
R=jpp@chromium.org

Review URL: https://codereview.chromium.org/1599803002 .

Provides a variant of the UnimplementedError macro specifically for use in incomplete target instruction lowering.  When --skip-unimplemented is specified, the UnimplementedLoweringError macro adds FakeUse and FakeDef instructions in order to maintain consistency in liveness analysis.

BUG= none
R=kschimpf@google.com

Review URL: https://codereview.chromium.org/1591893002 .

if vpush/vpop needs to emit multiple instructions (because of
non-consecutive registers), then the emitted sequence should be:

vpush list1
vpush list2
...
vpop list2
vpop list1

Subzero was emiting vpop in the wrong order:

vpop list1
vpop list2

These multiple lists push/pop arise because of the way fp32 and fp64
registers are declared (s0 -> s31, d31 -> d0).

This CL modifies fp64 registers so they are declared in ascending
order (d0 -> d31), which fixes subzero temporarily. The appropriate
fix is to change vpop to be emitted in the right order.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076
R=sehr@chromium.org, stichnot@chromium.org

Review URL: https://codereview.chromium.org/1592663004 .

This CL introduces the TargetLowering::AutoBundle type, which allows
RAII-style bundle emission. As part of the CL, all of the uses of
TargetLowering::_bundle_lock(), and TargetLowering::_bundle_unlock(),
were replaced with uses of the newly introduced type.

BUG=
R=sehr@chromium.org, stichnot@chromium.org

Review URL: https://codereview.chromium.org/1585843007 .

This allows better debugging of register encodings into
instructions, in the integrated assembler.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1571433004 .

A good trick for implementing lowering for a new target is, for not-yet-implemented instructions, to insert a FakeUse of each instruction variable followed by a FakeDef of the dest variable.  Otherwise one risks running afoul of liveness analysis integrity checks.

However, if all the high-level instructions in a basic block lack variables (e.g. unconditional branches, or void calls with only constant arguments), the resulting block may be completely empty.  In O2 mode, this triggers a couple of assertions/errors that wouldn't normally occur:

1. CfgNode::contractIfEmpty() finds a block with a single out-edge that does *not* end with an unconditional branch.

2. CfgNode::livenessAddIntervals() tries to add a bogus liveness interval to a variable because the empty block contains no actual instruction numbers to form a valid interval from.

This adds some fixes/workarounds for those problems.

Another workaround for the empty basic block problem may be to just to add a FakeUse of the stack pointer when lowering an unconditional branch, which combined with the trick above, should prevent empty blocks.  However, these fixes seem reasonable apart from that.

BUG= none
R=sehr@chromium.org

Review URL: https://codereview.chromium.org/1590303002 .