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  1. 07 Jan, 2016 5 commits
  3. 06 Jan, 2016 1 commit
    • Subzero: Enable Non-SFI vector cross tests. · 57a8aab2
      Jim Stichnoth authored 
      The driver programs for vector tests use a loop to initialize vector-type values one element at a time.  The PNaCl ABI requires the vector element index to be a constant, and the createConstantInsertExtractElementIndexPass() transformation creates an alloca instruction.  When this alloca is inside a loop, it can (and does in the cross tests) cause a stack overflow.

The workaround here is to use a noinline helper function to do the insertelement.

We didn't run into this problem until now because native and sandbox cross tests build the driver in a different way that presumably avoids running the PNaCl ABI simplification passes.

BUG= none
R=jpp@chromium.org

Review URL: https://codereview.chromium.org/1560933002 .
  5. 04 Jan, 2016 4 commits
    • Subzero: Add Non-SFI support for x86-32. · 8ff4b281
      Jim Stichnoth authored 
      The basic model is that each translated function begins with a special "GotVar = getIP" instruction, and each ConstantRelocatable reference is changed to GotVar+ConstantRelocatable@GOTOFF (assuming GotVar is legalized into a physical register).  The getIP instruction is late-lowered into:
  call __Sz_getIP_<reg>
  add <reg>, $_GLOBAL_OFFSET_TABLE_
  mov GotVar, <reg>
Note that _GLOBAL_OFFSET_TABLE_ gets a special relocation type.

The register allocator takes GotVar uses into account, giving appropriate weight toward register allocation.

If there are no uses of GotVar, the getIP instruction gets naturally dead-code eliminated.  Special treatment is needed to prevent this elimination when the only GotVar uses are for (floating point) constant pool values from Phi instructions, since the Phi lowering with its GotVar legalization happens after the main round of register allocation.

The x86 mem operand now has a IsPIC field to indicate whether it has been PIC-legalized.  Mem operands are sometimes legalized more than once, and this IsPIC field keeps GotVar from being added more than once.

We have to limit the aggressiveness of address mode inference, to make sure a register slot is left for the GotVar.

The Subzero runtime has new asm files to implement all possible __Sz_getIP_<reg> helpers.

The szbuild.py script and the spec2k version support Non-SFI builds.  Running spec2k depends on a pending change to the spec2k run_all.sh script.

Read-only data sections need to be named .data.rel.ro instead of .rodata because of PIC rules.

Most cross tests are working, but there is some problem with vector types that seems to be not Subzero related, so most vector tests are disabled for now.

Still to do:

* Fix "--nonsfi --filetype=iasm".  The llvm-mc assembler doesn't properly apply the _GLOBAL_OFFSET_TABLE_ relocation in iasm mode.  Maybe I can find a different syntactic trick that works, or use hybrid iasm for this limited case.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4327
R=jpp@chromium.org

Review URL: https://codereview.chromium.org/1506653002 .
    • Subzero. ARM32. Materializes the register table. · 149999e5
      John Porto authored 
      This CL modifies the ARM32 backend so that the REGARM32_TABLE is only
expanded once (to initialize a constexpr array.) This change decreased
the backend size in roughly ~80k.

BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076
R=kschimpf@google.com

Review URL: https://codereview.chromium.org/1554263002 .
    • Subzero. ARM32. Adds an IsGPR attribute to the register tables. · dff7dbdb
      John Porto authored 
      BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076
R=kschimpf@google.com

Review URL: https://codereview.chromium.org/1554203002 .
    • Subzero. Code organization. · 4a56686b
      John Porto authored 
      This CL does more than any CL should.

First, it moves all target-specific classes (TargetLowering, Assembler,
and Instructions) to a target-specific namespace. For example, the
::Ice::TargetX8632 class now lives in ::Ice::X8632::TargetX8632. Same
goes for ARM32, X8664, and MIPS32. Now, we have a ton of redundant
prefixes (it should be pretty obvious that ::Ice::X8632::TargetLowering
is an X8632 target lowering), but this is definitively not something
for this CL.

Second, this CL gets rid of the excessive use of 'typename Foo::Bar'
in the X86 templates. These changes appear more intimidating than they
really are, and they were fairly mechanical.

Third, the x86?? Traitses (gollum!) classes are no longer template
instatiation. The previous X86 templates were parameterized with a
X86 TargetLowering, and they assumed that a MachineTraits<Target>
was defined for that TargetLowering. The X86 templates are now
parameterized with a TraitsType, and different backends may have
completely unrelated traits.

Fourth, the X86 templates are no longer members of
::Ice::X86Internal. Instead, each file #include'ing a Ice*X86Base.h
file need to #define X86NAMESPACE to the namespace where the backend
is being defined. With this change, the template instantiation for
X8632 live in ::Ice::X8632, and, for X8664, in ::Ice::X8664.

BUG=
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1548363002 .
  7. 30 Dec, 2015 2 commits
    • Subzero. X86. Refactors initRegisterSet. · 4a308ced
      John Porto authored 
      initRegisterSet() for x8632 and x8664 were both huge. This CL refactors
those methods to use a pre-initialized table instead of the result of
expanding the x-macros.

BUG=
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1546373003 .
    • Subzero. Refactoring. · 53611e2c
      John Porto authored 
      This is the first step towards hiding backend-specific stuff from the
rest of subzero. In this CL, all the references to target-specific files
(e.g., IceTargetLoweringX8632.h) are removed from target-independent
files.

This CL also changes the named constructors in the Target-specific
classes (e.g., TargetX8632::create()) to return unique_ptrs.

BUG=
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1551633002 .
  9. 28 Dec, 2015 2 commits
    • misc cleanup of Compiler::run · 93d85ce0
      Reed Kotler authored 
      This assumes patch from 1534883005 though still needs to rename
validateAndGenerateBuildAttributes to  dumpBuildAttributes

BUG=
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1541063002 .

Patch from Reed Kotler <rkotlerimgtec@gmail.com>.
    • doxygenize IceClFlags.cpp · 2233987b
      Reed Kotler authored 
      This is a first cut at this. More can be done and much of this is just moving what is already in the help for the
commands into Doxygen comments. The documentation can be
expanded to better describe the role of the various
command line options.

BUG=
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1547743002 .

Patch from Reed Kotler <rkotlerimgtec@gmail.com>.
  11. 24 Dec, 2015 1 commit
  13. 22 Dec, 2015 2 commits
  15. 20 Dec, 2015 1 commit
  17. 18 Dec, 2015 9 commits
  19. 17 Dec, 2015 5 commits
  21. 16 Dec, 2015 5 commits
  23. 15 Dec, 2015 2 commits
  25. 14 Dec, 2015 1 commit